Details
Original language | English |
---|---|
Title of host publication | 2024 IEEE 30th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA) |
Pages | 91-96 |
Number of pages | 6 |
ISBN (electronic) | 979-8-3503-8795-7 |
Publication status | Published - 2024 |
Abstract
Synchronization of sensor devices is crucial for concurrent data acquisition. Numerous protocols have emerged for this task, and for some multi-sensor setups to operate synchronized, a conversion between deployed protocols is needed. This paper presents a bare-metal implementation of a Tri- Level Sync signal generator on a microcontroller unit (MCU) synchronized to a master clock via the IEEE 1588 Precision Time Protocol (PTP). Cameras can be synchronized by locking their frame generators to the Tri-Level Sync signal. As this synchronization depends on a stable analog signal, a careful design of the signal generation based on a PTP-managed clock is required. The limited tolerance of a camera to clock frequency adjustments for continuous operations imposes rate-limits on the PTP-controller. Simulations using a software model demonstrate the resulting controller instabilities from rate-limiting. This problem is addressed by introducing a linear prediction mode to the controller, which estimates the realizable offset change during rate-limited frequency alignment. By adjusting the frequency in a timely manner, a large overshoot of the controller can be avoided. Additionally, a cascading controller design that decouples the PTP from the clock update rate proved to be advantageous to increase the camera's tolerable frequency change. This paper demonstrates that a MCU is a viable platform to perform PTP-synchronized Tri-Level Sync generation. Our open source implementation is available for use by the research community at https://github.com/IMS-AS-LUH/t41-tri-sync-ptp.
Keywords
- MCU, PI-controller, PTP, Precision Time Protocol, SMPTE, Tri-Level Sync, camera, synchronization
ASJC Scopus subject areas
- Decision Sciences(all)
- Information Systems and Management
- Computer Science(all)
- Hardware and Architecture
- Computer Science(all)
- Computer Networks and Communications
- Computer Science(all)
- Computer Science Applications
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2024 IEEE 30th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA). 2024. p. 91-96.
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - PTP-Synchronized Tri-Level Sync Generation for Networked Multi-Sensor Systems
AU - Riggers, Christoph
AU - Schleusner, Jens
AU - Renke, Oliver
AU - Blume, Holger
N1 - Publisher Copyright: © 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - Synchronization of sensor devices is crucial for concurrent data acquisition. Numerous protocols have emerged for this task, and for some multi-sensor setups to operate synchronized, a conversion between deployed protocols is needed. This paper presents a bare-metal implementation of a Tri- Level Sync signal generator on a microcontroller unit (MCU) synchronized to a master clock via the IEEE 1588 Precision Time Protocol (PTP). Cameras can be synchronized by locking their frame generators to the Tri-Level Sync signal. As this synchronization depends on a stable analog signal, a careful design of the signal generation based on a PTP-managed clock is required. The limited tolerance of a camera to clock frequency adjustments for continuous operations imposes rate-limits on the PTP-controller. Simulations using a software model demonstrate the resulting controller instabilities from rate-limiting. This problem is addressed by introducing a linear prediction mode to the controller, which estimates the realizable offset change during rate-limited frequency alignment. By adjusting the frequency in a timely manner, a large overshoot of the controller can be avoided. Additionally, a cascading controller design that decouples the PTP from the clock update rate proved to be advantageous to increase the camera's tolerable frequency change. This paper demonstrates that a MCU is a viable platform to perform PTP-synchronized Tri-Level Sync generation. Our open source implementation is available for use by the research community at https://github.com/IMS-AS-LUH/t41-tri-sync-ptp.
AB - Synchronization of sensor devices is crucial for concurrent data acquisition. Numerous protocols have emerged for this task, and for some multi-sensor setups to operate synchronized, a conversion between deployed protocols is needed. This paper presents a bare-metal implementation of a Tri- Level Sync signal generator on a microcontroller unit (MCU) synchronized to a master clock via the IEEE 1588 Precision Time Protocol (PTP). Cameras can be synchronized by locking their frame generators to the Tri-Level Sync signal. As this synchronization depends on a stable analog signal, a careful design of the signal generation based on a PTP-managed clock is required. The limited tolerance of a camera to clock frequency adjustments for continuous operations imposes rate-limits on the PTP-controller. Simulations using a software model demonstrate the resulting controller instabilities from rate-limiting. This problem is addressed by introducing a linear prediction mode to the controller, which estimates the realizable offset change during rate-limited frequency alignment. By adjusting the frequency in a timely manner, a large overshoot of the controller can be avoided. Additionally, a cascading controller design that decouples the PTP from the clock update rate proved to be advantageous to increase the camera's tolerable frequency change. This paper demonstrates that a MCU is a viable platform to perform PTP-synchronized Tri-Level Sync generation. Our open source implementation is available for use by the research community at https://github.com/IMS-AS-LUH/t41-tri-sync-ptp.
KW - MCU
KW - PI-controller
KW - PTP
KW - Precision Time Protocol
KW - SMPTE
KW - Tri-Level Sync
KW - camera
KW - synchronization
UR - http://www.scopus.com/inward/record.url?scp=85207070117&partnerID=8YFLogxK
U2 - 10.1109/rtcsa62462.2024.00022
DO - 10.1109/rtcsa62462.2024.00022
M3 - Conference contribution
SN - 979-8-3503-8796-4
SP - 91
EP - 96
BT - 2024 IEEE 30th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)
ER -