Details
| Original language | English |
|---|---|
| Title of host publication | 2007 International Conference on Embedded Computer Systems |
| Subtitle of host publication | Architectures, Modeling and Simulation |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 74-81 |
| Number of pages | 8 |
| ISBN (print) | 1424410584 |
| Publication status | Published - 8 Aug 2007 |
| Externally published | Yes |
| Event | 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2007 - Samos, Greece Duration: 16 Jul 2007 → 19 Jul 2007 |
Abstract
In this contribution, the potential of parallelized software that implements algorithms of digital signal processing on a multicore processor platform is analyzed. For this purpose various digital signal processing tasks have been implemented on a prototyping platform i.e. an ARM MPCore featuring four ARM11 processor cores. In order to analyze the effect of parallelization on the resulting performance-power ratio, influencing parameters like e.g. the number of issued program threads have been studied. For parallelization issues the OpenMP programming model has been used which can be efficiently applied on C-level. In order to elaborate power efficient code also a functional and instruction level power model of the MPCore has been derived which features a high estimation accuracy. Using this power model and exploiting the capabilities of OpenMP a variety of exemplary tasks could be efficiently parallelized. The general efficiency potential of parallelization for multiprocessor architectures can be assembled.
Keywords
- Multicore processors, Parallelization, Power estimation and optimization
ASJC Scopus subject areas
- Computer Science(all)
- General Computer Science
- Computer Science(all)
- Hardware and Architecture
- Engineering(all)
- Control and Systems Engineering
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2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation. Institute of Electrical and Electronics Engineers Inc., 2007. p. 74-81.
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - Performance and Power Analysis of Parallelized Implementations on an MPCore Multiprocessor Platform
AU - Blume, H.
AU - Livonius, J. V.
AU - Rotenberg, L.
AU - Noll, T. G.
AU - Bothe, H.
AU - Brakensiek, J.
PY - 2007/8/8
Y1 - 2007/8/8
N2 - In this contribution, the potential of parallelized software that implements algorithms of digital signal processing on a multicore processor platform is analyzed. For this purpose various digital signal processing tasks have been implemented on a prototyping platform i.e. an ARM MPCore featuring four ARM11 processor cores. In order to analyze the effect of parallelization on the resulting performance-power ratio, influencing parameters like e.g. the number of issued program threads have been studied. For parallelization issues the OpenMP programming model has been used which can be efficiently applied on C-level. In order to elaborate power efficient code also a functional and instruction level power model of the MPCore has been derived which features a high estimation accuracy. Using this power model and exploiting the capabilities of OpenMP a variety of exemplary tasks could be efficiently parallelized. The general efficiency potential of parallelization for multiprocessor architectures can be assembled.
AB - In this contribution, the potential of parallelized software that implements algorithms of digital signal processing on a multicore processor platform is analyzed. For this purpose various digital signal processing tasks have been implemented on a prototyping platform i.e. an ARM MPCore featuring four ARM11 processor cores. In order to analyze the effect of parallelization on the resulting performance-power ratio, influencing parameters like e.g. the number of issued program threads have been studied. For parallelization issues the OpenMP programming model has been used which can be efficiently applied on C-level. In order to elaborate power efficient code also a functional and instruction level power model of the MPCore has been derived which features a high estimation accuracy. Using this power model and exploiting the capabilities of OpenMP a variety of exemplary tasks could be efficiently parallelized. The general efficiency potential of parallelization for multiprocessor architectures can be assembled.
KW - Multicore processors
KW - Parallelization
KW - Power estimation and optimization
UR - http://www.scopus.com/inward/record.url?scp=47749108744&partnerID=8YFLogxK
U2 - 10.1109/ICSAMOS.2007.4285736
DO - 10.1109/ICSAMOS.2007.4285736
M3 - Conference contribution
AN - SCOPUS:47749108744
SN - 1424410584
SP - 74
EP - 81
BT - 2007 International Conference on Embedded Computer Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2007
Y2 - 16 July 2007 through 19 July 2007
ER -