Equivalence Checking Methods for Analog Circuits Using Continuous Reachable Sets.

Research output: Chapter in book/report/conference proceedingConference contributionResearchpeer review

Authors

  • Ahmad Tarraf
  • Lars Hedrich
  • Niklas Kochdumper
  • Malgorzata Rechmal-Lesse
  • Markus Olbrich

Research Organisations

External Research Organisations

  • Goethe University Frankfurt
  • Technical University of Munich (TUM)
View graph of relations

Details

Original languageEnglish
Title of host publication2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pages7-12
Number of pages6
ISBN (electronic)9781728157757
Publication statusPublished - 2020

Publication series

NameProceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Volume2020-July
ISSN (Print)2159-3469
ISSN (electronic)2159-3477

Abstract

In this paper, we propose a new methodology for equivalence checking in the AMS domain. On top of comparing two existing approaches, we define a new methodology using continuous reachable sets. The approaches are illustrated upon two existing abstract modeling techniques. Moreover, the generated models are compared against a conformant model that captures the measured system behavior from the real circuit. These modeling methodologies yield hybrid automatons (HAs), which along with the netlist, are compared using different equivalence checking methods demonstrating verification techniques on different abstraction levels. Finally, we discuss the methodologies with respect to an efficient and safe circuit design.

Keywords

    AMS verification, Behavioral modeling, Coverage, Equivalence checking, Hybrid automata, Reachability

ASJC Scopus subject areas

Cite this

Equivalence Checking Methods for Analog Circuits Using Continuous Reachable Sets. / Tarraf, Ahmad; Hedrich, Lars; Kochdumper, Niklas et al.
2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). 2020. p. 7-12 9154965 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2020-July).

Research output: Chapter in book/report/conference proceedingConference contributionResearchpeer review

Tarraf, A, Hedrich, L, Kochdumper, N, Rechmal-Lesse, M & Olbrich, M 2020, Equivalence Checking Methods for Analog Circuits Using Continuous Reachable Sets. in 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)., 9154965, Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, vol. 2020-July, pp. 7-12. https://doi.org/10.1109/isvlsi49217.2020.00012
Tarraf, A., Hedrich, L., Kochdumper, N., Rechmal-Lesse, M., & Olbrich, M. (2020). Equivalence Checking Methods for Analog Circuits Using Continuous Reachable Sets. In 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (pp. 7-12). Article 9154965 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2020-July). https://doi.org/10.1109/isvlsi49217.2020.00012
Tarraf A, Hedrich L, Kochdumper N, Rechmal-Lesse M, Olbrich M. Equivalence Checking Methods for Analog Circuits Using Continuous Reachable Sets. In 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). 2020. p. 7-12. 9154965. (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI). doi: 10.1109/isvlsi49217.2020.00012
Tarraf, Ahmad ; Hedrich, Lars ; Kochdumper, Niklas et al. / Equivalence Checking Methods for Analog Circuits Using Continuous Reachable Sets. 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). 2020. pp. 7-12 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI).
Download
@inproceedings{1c38bf552bf54a7490e76f27b1777c22,
title = "Equivalence Checking Methods for Analog Circuits Using Continuous Reachable Sets.",
abstract = "In this paper, we propose a new methodology for equivalence checking in the AMS domain. On top of comparing two existing approaches, we define a new methodology using continuous reachable sets. The approaches are illustrated upon two existing abstract modeling techniques. Moreover, the generated models are compared against a conformant model that captures the measured system behavior from the real circuit. These modeling methodologies yield hybrid automatons (HAs), which along with the netlist, are compared using different equivalence checking methods demonstrating verification techniques on different abstraction levels. Finally, we discuss the methodologies with respect to an efficient and safe circuit design.",
keywords = "AMS verification, Behavioral modeling, Coverage, Equivalence checking, Hybrid automata, Reachability",
author = "Ahmad Tarraf and Lars Hedrich and Niklas Kochdumper and Malgorzata Rechmal-Lesse and Markus Olbrich",
year = "2020",
doi = "10.1109/isvlsi49217.2020.00012",
language = "English",
isbn = "978-1-7281-5776-4",
series = "Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI",
pages = "7--12",
booktitle = "2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)",

}

Download

TY - GEN

T1 - Equivalence Checking Methods for Analog Circuits Using Continuous Reachable Sets.

AU - Tarraf, Ahmad

AU - Hedrich, Lars

AU - Kochdumper, Niklas

AU - Rechmal-Lesse, Malgorzata

AU - Olbrich, Markus

PY - 2020

Y1 - 2020

N2 - In this paper, we propose a new methodology for equivalence checking in the AMS domain. On top of comparing two existing approaches, we define a new methodology using continuous reachable sets. The approaches are illustrated upon two existing abstract modeling techniques. Moreover, the generated models are compared against a conformant model that captures the measured system behavior from the real circuit. These modeling methodologies yield hybrid automatons (HAs), which along with the netlist, are compared using different equivalence checking methods demonstrating verification techniques on different abstraction levels. Finally, we discuss the methodologies with respect to an efficient and safe circuit design.

AB - In this paper, we propose a new methodology for equivalence checking in the AMS domain. On top of comparing two existing approaches, we define a new methodology using continuous reachable sets. The approaches are illustrated upon two existing abstract modeling techniques. Moreover, the generated models are compared against a conformant model that captures the measured system behavior from the real circuit. These modeling methodologies yield hybrid automatons (HAs), which along with the netlist, are compared using different equivalence checking methods demonstrating verification techniques on different abstraction levels. Finally, we discuss the methodologies with respect to an efficient and safe circuit design.

KW - AMS verification

KW - Behavioral modeling

KW - Coverage

KW - Equivalence checking

KW - Hybrid automata

KW - Reachability

UR - http://www.scopus.com/inward/record.url?scp=85090407694&partnerID=8YFLogxK

U2 - 10.1109/isvlsi49217.2020.00012

DO - 10.1109/isvlsi49217.2020.00012

M3 - Conference contribution

SN - 978-1-7281-5776-4

T3 - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

SP - 7

EP - 12

BT - 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

ER -