Details
| Original language | English |
|---|---|
| Title of host publication | Embedded Computer Systems |
| Subtitle of host publication | Architectures, Modeling, and Simulation - 24th International Conference, SAMOS 2024, Proceedings |
| Editors | Luigi Carro, Francesco Regazzoni, Christian Pilato |
| Publisher | Springer Science and Business Media Deutschland GmbH |
| Pages | 167-182 |
| Number of pages | 16 |
| ISBN (electronic) | 978-3-031-78377-7 |
| ISBN (print) | 9783031783760 |
| Publication status | Published - 28 Jan 2025 |
| Event | 24th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2024 - Samos, Greece Duration: 29 Jun 2024 → 4 Jul 2024 |
Publication series
| Name | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) |
|---|---|
| Volume | 15226 LNCS |
| ISSN (Print) | 0302-9743 |
| ISSN (electronic) | 1611-3349 |
Abstract
Efficient processing architectures for irregular data patterns require vector element addressing with flexible indices. Therefore, state-of-the-art SIMD vector extensions implement gather and scatter instructions for indexed addressing of data in memory. In vertical vector processors, different data is processed sequentially in parallel lanes and can be exchanged via chaining. This paper proposes an extension of such chaining mechanisms in a vertical vector processor architecture (V2PRO) to flexibly chain not only data but also address offsets between vector lanes. The indirect addressing enables vector access patterns with irregular strides for both register file and memory. The extension has a low hardware overhead of +4.8 % lookup tables and +1.8% registers on a Xilinx Ultrascale+ FPGA. A runtime evaluation for two applications from computer vision, namely Deformable Convolutions and point cloud encoding with PointPillars, demonstrates speedups of at least an order of magnitude with the proposed extension.
Keywords
- Computer Vision, Indirect Addressing Mode, Radar Object Detection, Vector Processor Architecture
ASJC Scopus subject areas
- Mathematics(all)
- Theoretical Computer Science
- Computer Science(all)
- General Computer Science
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Embedded Computer Systems: Architectures, Modeling, and Simulation - 24th International Conference, SAMOS 2024, Proceedings. ed. / Luigi Carro; Francesco Regazzoni; Christian Pilato. Springer Science and Business Media Deutschland GmbH, 2025. p. 167-182 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 15226 LNCS).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - A Novel Chaining-Based Indirect Addressing Mode in a Vertical Vector Processor
AU - Gesper, Sven
AU - Köhler, Daniel
AU - Thieu, Gia Bao
AU - Homann, Jasper
AU - Meinl, Frank
AU - Blume, Holger
AU - Payá-Vayá, Guillermo
N1 - Publisher Copyright: © The Author(s), under exclusive license to Springer Nature Switzerland AG 2025.
PY - 2025/1/28
Y1 - 2025/1/28
N2 - Efficient processing architectures for irregular data patterns require vector element addressing with flexible indices. Therefore, state-of-the-art SIMD vector extensions implement gather and scatter instructions for indexed addressing of data in memory. In vertical vector processors, different data is processed sequentially in parallel lanes and can be exchanged via chaining. This paper proposes an extension of such chaining mechanisms in a vertical vector processor architecture (V2PRO) to flexibly chain not only data but also address offsets between vector lanes. The indirect addressing enables vector access patterns with irregular strides for both register file and memory. The extension has a low hardware overhead of +4.8 % lookup tables and +1.8% registers on a Xilinx Ultrascale+ FPGA. A runtime evaluation for two applications from computer vision, namely Deformable Convolutions and point cloud encoding with PointPillars, demonstrates speedups of at least an order of magnitude with the proposed extension.
AB - Efficient processing architectures for irregular data patterns require vector element addressing with flexible indices. Therefore, state-of-the-art SIMD vector extensions implement gather and scatter instructions for indexed addressing of data in memory. In vertical vector processors, different data is processed sequentially in parallel lanes and can be exchanged via chaining. This paper proposes an extension of such chaining mechanisms in a vertical vector processor architecture (V2PRO) to flexibly chain not only data but also address offsets between vector lanes. The indirect addressing enables vector access patterns with irregular strides for both register file and memory. The extension has a low hardware overhead of +4.8 % lookup tables and +1.8% registers on a Xilinx Ultrascale+ FPGA. A runtime evaluation for two applications from computer vision, namely Deformable Convolutions and point cloud encoding with PointPillars, demonstrates speedups of at least an order of magnitude with the proposed extension.
KW - Computer Vision
KW - Indirect Addressing Mode
KW - Radar Object Detection
KW - Vector Processor Architecture
UR - http://www.scopus.com/inward/record.url?scp=85218467582&partnerID=8YFLogxK
U2 - 10.1007/978-3-031-78377-7_12
DO - 10.1007/978-3-031-78377-7_12
M3 - Conference contribution
AN - SCOPUS:85218467582
SN - 9783031783760
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 167
EP - 182
BT - Embedded Computer Systems
A2 - Carro, Luigi
A2 - Regazzoni, Francesco
A2 - Pilato, Christian
PB - Springer Science and Business Media Deutschland GmbH
T2 - 24th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2024
Y2 - 29 June 2024 through 4 July 2024
ER -