A DAC Sharing and Linearization Technique for Time-Interleaved Incremental Delta-Sigma ADCs

Research output: Chapter in book/report/conference proceedingConference contributionResearchpeer review

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Research Organisations

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  • University of Applied Sciences and Arts Hannover (HsH)
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Details

Original languageEnglish
Title of host publicationISCAS 2024 - IEEE International Symposium on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages5
ISBN (electronic)9798350330991
ISBN (print)979-8-3503-3100-4
Publication statusPublished - 2024
Event2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024 - , Singapore
Duration: 19 May 202422 May 2024

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Abstract

This paper presents a digital-to-analog converter (DAC) sharing method for time-interleaved (TI)-incremental delta-sigma modulators (I-ΔΣMs), which allows significant savings of passives by 40 % in the DACs. The proposed DAC sharing shows an increased robustness to nonlinearities and is further adapted to a linearization technique known from non-TI-I-ΔΣMs. The paper extends the known linearization technique to achieve optimal signal to noise and distortion ratio (SNDR) across the modulator's entire dynamic range (DR). An increase of 7 dB in SNDR is demonstrated for low input signals powers, which has not been shown before. It is demonstrated, that the high linearity of the system allows to compensate for the gain mismatch in TI operation with a simple gain factor to retain near ideal performance. Furthermore, the paper proposes a practical circuit implementation for the shared DAC and a correlation based error estimation to determine the channel gain mismatch.

Keywords

    analog-to-digital converter, hardware-sharing, incremental delta-sigma modulator, linearization, time-interleaved

ASJC Scopus subject areas

Cite this

A DAC Sharing and Linearization Technique for Time-Interleaved Incremental Delta-Sigma ADCs. / Flemming, Jesko; Wicht, Bernhard; Witte, Pascal.
ISCAS 2024 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 2024. (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in book/report/conference proceedingConference contributionResearchpeer review

Flemming, J, Wicht, B & Witte, P 2024, A DAC Sharing and Linearization Technique for Time-Interleaved Incremental Delta-Sigma ADCs. in ISCAS 2024 - IEEE International Symposium on Circuits and Systems. Proceedings - IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers Inc., 2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024, Singapore, 19 May 2024. https://doi.org/10.1109/ISCAS58744.2024.10557987
Flemming, J., Wicht, B., & Witte, P. (2024). A DAC Sharing and Linearization Technique for Time-Interleaved Incremental Delta-Sigma ADCs. In ISCAS 2024 - IEEE International Symposium on Circuits and Systems (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS58744.2024.10557987
Flemming J, Wicht B, Witte P. A DAC Sharing and Linearization Technique for Time-Interleaved Incremental Delta-Sigma ADCs. In ISCAS 2024 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc. 2024. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS58744.2024.10557987
Flemming, Jesko ; Wicht, Bernhard ; Witte, Pascal. / A DAC Sharing and Linearization Technique for Time-Interleaved Incremental Delta-Sigma ADCs. ISCAS 2024 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 2024. (Proceedings - IEEE International Symposium on Circuits and Systems).
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abstract = "This paper presents a digital-to-analog converter (DAC) sharing method for time-interleaved (TI)-incremental delta-sigma modulators (I-ΔΣMs), which allows significant savings of passives by 40 % in the DACs. The proposed DAC sharing shows an increased robustness to nonlinearities and is further adapted to a linearization technique known from non-TI-I-ΔΣMs. The paper extends the known linearization technique to achieve optimal signal to noise and distortion ratio (SNDR) across the modulator's entire dynamic range (DR). An increase of 7 dB in SNDR is demonstrated for low input signals powers, which has not been shown before. It is demonstrated, that the high linearity of the system allows to compensate for the gain mismatch in TI operation with a simple gain factor to retain near ideal performance. Furthermore, the paper proposes a practical circuit implementation for the shared DAC and a correlation based error estimation to determine the channel gain mismatch.",
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AU - Flemming, Jesko

AU - Wicht, Bernhard

AU - Witte, Pascal

N1 - Publisher Copyright: © 2024 IEEE.

PY - 2024

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N2 - This paper presents a digital-to-analog converter (DAC) sharing method for time-interleaved (TI)-incremental delta-sigma modulators (I-ΔΣMs), which allows significant savings of passives by 40 % in the DACs. The proposed DAC sharing shows an increased robustness to nonlinearities and is further adapted to a linearization technique known from non-TI-I-ΔΣMs. The paper extends the known linearization technique to achieve optimal signal to noise and distortion ratio (SNDR) across the modulator's entire dynamic range (DR). An increase of 7 dB in SNDR is demonstrated for low input signals powers, which has not been shown before. It is demonstrated, that the high linearity of the system allows to compensate for the gain mismatch in TI operation with a simple gain factor to retain near ideal performance. Furthermore, the paper proposes a practical circuit implementation for the shared DAC and a correlation based error estimation to determine the channel gain mismatch.

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