3-D placement considering vertical interconnects

Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review

Authors

  • I. Kaya
  • M. Olbrich
  • E. Barke

Research Organisations

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Details

Original languageEnglish
Title of host publicationProceedings - IEEE International SOC Conference, SOCC 2003
EditorsDong S. Ha, Richard Auletta, John Chickanosky
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages257-258
Number of pages2
ISBN (electronic)0780381823, 9780780381827
Publication statusPublished - 2003
EventIEEE International SOC Conference, SOCC 2003 - Portland, United States
Duration: 17 Sept 2003 → 20 Sept 2003

Publication series

NameProceedings - IEEE International SOC Conference, SOCC 2003

Abstract

3D integration is going to play an important role in the future. Increasing complexity and increasing impact of interconnects to integrated circuit (IC) performance makes 3D more and more attractive. EDA tools for 3D design hardly exist. We propose a new 3D standard-cell placer based on quadratic programming. It ensures a reduction of the total wirelength and can deal with standard cells and vertical interconnects simultaneously. The final result is a legalized, design rule compliant and discrete 3D placement.

Keywords

    CMOS technology, Delay, Electronic design automation and methodology, Integrated circuit interconnections, Microelectronics, Nonlinear equations, Routing, Vectors, Very large scale integration

ASJC Scopus subject areas

Cite this

3-D placement considering vertical interconnects. / Kaya, I.; Olbrich, M.; Barke, E.
Proceedings - IEEE International SOC Conference, SOCC 2003. ed. / Dong S. Ha; Richard Auletta; John Chickanosky. Institute of Electrical and Electronics Engineers Inc., 2003. p. 257-258 1241509 (Proceedings - IEEE International SOC Conference, SOCC 2003).

Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review

Kaya, I, Olbrich, M & Barke, E 2003, 3-D placement considering vertical interconnects. in DS Ha, R Auletta & J Chickanosky (eds), Proceedings - IEEE International SOC Conference, SOCC 2003., 1241509, Proceedings - IEEE International SOC Conference, SOCC 2003, Institute of Electrical and Electronics Engineers Inc., pp. 257-258, IEEE International SOC Conference, SOCC 2003, Portland, United States, 17 Sept 2003. https://doi.org/10.1109/SOC.2003.1241509
Kaya, I., Olbrich, M., & Barke, E. (2003). 3-D placement considering vertical interconnects. In D. S. Ha, R. Auletta, & J. Chickanosky (Eds.), Proceedings - IEEE International SOC Conference, SOCC 2003 (pp. 257-258). Article 1241509 (Proceedings - IEEE International SOC Conference, SOCC 2003). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SOC.2003.1241509
Kaya I, Olbrich M, Barke E. 3-D placement considering vertical interconnects. In Ha DS, Auletta R, Chickanosky J, editors, Proceedings - IEEE International SOC Conference, SOCC 2003. Institute of Electrical and Electronics Engineers Inc. 2003. p. 257-258. 1241509. (Proceedings - IEEE International SOC Conference, SOCC 2003). doi: 10.1109/SOC.2003.1241509
Kaya, I. ; Olbrich, M. ; Barke, E. / 3-D placement considering vertical interconnects. Proceedings - IEEE International SOC Conference, SOCC 2003. editor / Dong S. Ha ; Richard Auletta ; John Chickanosky. Institute of Electrical and Electronics Engineers Inc., 2003. pp. 257-258 (Proceedings - IEEE International SOC Conference, SOCC 2003).
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