Details
| Original language | English |
|---|---|
| Title of host publication | IECON 2006 |
| Subtitle of host publication | 32nd Annual Conference on IEEE Industrial Electronics |
| Pages | 1082-1088 |
| Number of pages | 7 |
| Publication status | Published - 2006 |
| Event | IECON 2006 - 32nd Annual Conference on IEEE Industrial Electronics - Paris, France Duration: 6 Nov 2006 → 10 Nov 2006 |
Publication series
| Name | IECON Proceedings (Industrial Electronics Conference) |
|---|
Abstract
This paper presents a detailed analysis and optimisation of output Alters for inverter fed drives. The goal is to minimise the total cost of the Alter components when the maximum deviation of the fundamental output voltage and the minimum suppression of harmonic voltages are given. The analysis is based on the full equivalent circuit diagram of induction machines and thus covers all possible load states of the drive. Besides simple LC Alters, a fourth order LCLC Alter and an LC Alter with additional band rejection are discussed.
ASJC Scopus subject areas
- Engineering(all)
- Control and Systems Engineering
- Engineering(all)
- Electrical and Electronic Engineering
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IECON 2006 : 32nd Annual Conference on IEEE Industrial Electronics. 2006. p. 1082-1088 4153230 (IECON Proceedings (Industrial Electronics Conference)).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - Optimisation of output filters for inverter fed drives
AU - Pöhler, S.
AU - Mertens, A.
AU - Sommer, R.
PY - 2006
Y1 - 2006
N2 - This paper presents a detailed analysis and optimisation of output Alters for inverter fed drives. The goal is to minimise the total cost of the Alter components when the maximum deviation of the fundamental output voltage and the minimum suppression of harmonic voltages are given. The analysis is based on the full equivalent circuit diagram of induction machines and thus covers all possible load states of the drive. Besides simple LC Alters, a fourth order LCLC Alter and an LC Alter with additional band rejection are discussed.
AB - This paper presents a detailed analysis and optimisation of output Alters for inverter fed drives. The goal is to minimise the total cost of the Alter components when the maximum deviation of the fundamental output voltage and the minimum suppression of harmonic voltages are given. The analysis is based on the full equivalent circuit diagram of induction machines and thus covers all possible load states of the drive. Besides simple LC Alters, a fourth order LCLC Alter and an LC Alter with additional band rejection are discussed.
UR - http://www.scopus.com/inward/record.url?scp=50249113091&partnerID=8YFLogxK
U2 - 10.1109/IECON.2006.347319
DO - 10.1109/IECON.2006.347319
M3 - Conference contribution
AN - SCOPUS:50249113091
SN - 1424401364
SN - 9781424401369
T3 - IECON Proceedings (Industrial Electronics Conference)
SP - 1082
EP - 1088
BT - IECON 2006
T2 - IECON 2006 - 32nd Annual Conference on IEEE Industrial Electronics
Y2 - 6 November 2006 through 10 November 2006
ER -