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High Temperature In-Order RISC-V Processor with Heterogeneous Pipeline and Out-of-Order Write-Back Mechanism

Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review

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  1. 2024

  2. Published

    Optimizing RISC-V Processor Performance with Adaptive Execution Unit Lengths in Harsh Environment Conditio

    Szücs, J., Hawich, M. & Blume, H. C., 2024, 2024 Panhellenic Conference on Electronics & Telecommunications (PACET). p. 1-5 5 p.

    Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review