Details
| Original language | English |
|---|---|
| Pages (from-to) | 31-43 |
| Number of pages | 13 |
| Journal | Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology |
| Volume | 22 |
| Issue number | 1 |
| Publication status | Published - 1 Aug 1999 |
| Externally published | Yes |
Abstract
This paper describes a new architecture for JAVA-based, interactive multimedia applications. A hardware implementation of a Java Virtual Machine (JVM) is proposed, which allows the direct execution of Java bytecode. In a single clock cycle, up to 3 bytecode instructions can be decoded and executed in parallel using a RISC pipeline. A splitable 64-bit ALU implementation addresses demanding processing requirements of typical multimedia signal processing schemes. The on-chip caches are adapted to the specific data structures of the JVM. The proposed architecture supports execution of multiple Java threads in parallel. An implementation of basic building blocks of the processor with a standard-cell library provides an estimate of 150 MHz clock-speed for a 0.35 μm 3 metal layer CMOS process. With a size of less than 10 mm2 needed for the core logic, it is possible to integrate multiple JVMs together with larger cache memories on a single chip. Based on these results, we discuss various performance aspects of JAVA for use in future multimedia terminals.
ASJC Scopus subject areas
- Computer Science(all)
- Signal Processing
- Computer Science(all)
- Information Systems
- Engineering(all)
- Electrical and Electronic Engineering
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In: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, Vol. 22, No. 1, 01.08.1999, p. 31-43.
Research output: Contribution to journal › Article › Research › peer review
}
TY - JOUR
T1 - Hardware realization of a Java Virtual Machine for high performance multimedia applications
AU - Berekovic, Mladen
AU - Kloos, Helge
AU - Pirsch, Peter
PY - 1999/8/1
Y1 - 1999/8/1
N2 - This paper describes a new architecture for JAVA-based, interactive multimedia applications. A hardware implementation of a Java Virtual Machine (JVM) is proposed, which allows the direct execution of Java bytecode. In a single clock cycle, up to 3 bytecode instructions can be decoded and executed in parallel using a RISC pipeline. A splitable 64-bit ALU implementation addresses demanding processing requirements of typical multimedia signal processing schemes. The on-chip caches are adapted to the specific data structures of the JVM. The proposed architecture supports execution of multiple Java threads in parallel. An implementation of basic building blocks of the processor with a standard-cell library provides an estimate of 150 MHz clock-speed for a 0.35 μm 3 metal layer CMOS process. With a size of less than 10 mm2 needed for the core logic, it is possible to integrate multiple JVMs together with larger cache memories on a single chip. Based on these results, we discuss various performance aspects of JAVA for use in future multimedia terminals.
AB - This paper describes a new architecture for JAVA-based, interactive multimedia applications. A hardware implementation of a Java Virtual Machine (JVM) is proposed, which allows the direct execution of Java bytecode. In a single clock cycle, up to 3 bytecode instructions can be decoded and executed in parallel using a RISC pipeline. A splitable 64-bit ALU implementation addresses demanding processing requirements of typical multimedia signal processing schemes. The on-chip caches are adapted to the specific data structures of the JVM. The proposed architecture supports execution of multiple Java threads in parallel. An implementation of basic building blocks of the processor with a standard-cell library provides an estimate of 150 MHz clock-speed for a 0.35 μm 3 metal layer CMOS process. With a size of less than 10 mm2 needed for the core logic, it is possible to integrate multiple JVMs together with larger cache memories on a single chip. Based on these results, we discuss various performance aspects of JAVA for use in future multimedia terminals.
UR - http://www.scopus.com/inward/record.url?scp=0032646314&partnerID=8YFLogxK
U2 - 10.1023/A:1008169702146
DO - 10.1023/A:1008169702146
M3 - Article
AN - SCOPUS:0032646314
VL - 22
SP - 31
EP - 43
JO - Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
JF - Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
SN - 0922-5773
IS - 1
ER -