Details
| Original language | English |
|---|---|
| Title of host publication | 91 Int Conf Wafer Scale Integr |
| Pages | 19-25 |
| Number of pages | 7 |
| Publication status | Published - 1991 |
| Event | 1991 International Conference on Wafer Scale Integration - San Francisco, CA, USA Duration: 29 Jan 1991 → 31 Jan 1991 |
Publication series
| Name | 91 Int Conf Wafer Scale Integr |
|---|
Abstract
A defect-tolerant, advanced VLSI-implementation of the two-dimensional convolution algorithm for real-time processing is presented. The chip contrasts with previously published convolution chips by its maximum mask size of 256 tabs (dividable into up to four independent masks which were applied to the same video-signal) support of adaptive filtering, on-chip delay-lines, and implemented special processing of frame-borders. Yield-enhancement techniques and architectural concepts for the design of large-area chips have been investigated and applied to the chip-design. Yield calculations show that, by the combination of new architectural concepts, effective hierarchical reconfiguration schemes, layout redundancies, and design of global parts using conservative design-rules, a high yield increase (67%) with low area overhead (6%) has been achieved.
ASJC Scopus subject areas
- Engineering(all)
- General Engineering
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91 Int Conf Wafer Scale Integr. 1991. p. 19-25 (91 Int Conf Wafer Scale Integr).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - Defect-tolerant implementation of a systolic array for two-dimensional convolution
AU - Ronner, Karsten
AU - Hecht, Volker
AU - Pirsch, Peter
PY - 1991
Y1 - 1991
N2 - A defect-tolerant, advanced VLSI-implementation of the two-dimensional convolution algorithm for real-time processing is presented. The chip contrasts with previously published convolution chips by its maximum mask size of 256 tabs (dividable into up to four independent masks which were applied to the same video-signal) support of adaptive filtering, on-chip delay-lines, and implemented special processing of frame-borders. Yield-enhancement techniques and architectural concepts for the design of large-area chips have been investigated and applied to the chip-design. Yield calculations show that, by the combination of new architectural concepts, effective hierarchical reconfiguration schemes, layout redundancies, and design of global parts using conservative design-rules, a high yield increase (67%) with low area overhead (6%) has been achieved.
AB - A defect-tolerant, advanced VLSI-implementation of the two-dimensional convolution algorithm for real-time processing is presented. The chip contrasts with previously published convolution chips by its maximum mask size of 256 tabs (dividable into up to four independent masks which were applied to the same video-signal) support of adaptive filtering, on-chip delay-lines, and implemented special processing of frame-borders. Yield-enhancement techniques and architectural concepts for the design of large-area chips have been investigated and applied to the chip-design. Yield calculations show that, by the combination of new architectural concepts, effective hierarchical reconfiguration schemes, layout redundancies, and design of global parts using conservative design-rules, a high yield increase (67%) with low area overhead (6%) has been achieved.
UR - http://www.scopus.com/inward/record.url?scp=0025839976&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0025839976
SN - 0818691263
T3 - 91 Int Conf Wafer Scale Integr
SP - 19
EP - 25
BT - 91 Int Conf Wafer Scale Integr
T2 - 1991 International Conference on Wafer Scale Integration
Y2 - 29 January 1991 through 31 January 1991
ER -