Details
| Original language | English |
|---|---|
| Pages (from-to) | 225-231 |
| Number of pages | 7 |
| Journal | IEEE International Test Conference (TC) |
| Publication status | Published - 1 Dec 1996 |
| Event | 1996 IEEE International Test Conference (ITC): Test and Design Validity - Washington, DC, USA Duration: 20 Oct 1996 → 25 Oct 1996 |
Abstract
This paper presents a Scan path design to ease the controllability and observability of Self-timed logic. The Scan path registers operate in asynchronous mode during operation and test. Therefore, no synchronous test clock is necessary during the test mode. New test control modules provide the control sequences to switch between the parallel data path and the serial Scan path. In addition to the data path, the control path and the bundled data interface is integrated into the test concept. The new Scan path register has been developed with low area overhead and a small additional delay in the critical data path. An example is used to verify this DFT modules for the data and the control path. It demonstrates the functionality during test and operational made and the compact realization of the asynchronous scan register.
ASJC Scopus subject areas
- Engineering(all)
- Electrical and Electronic Engineering
- Mathematics(all)
- Applied Mathematics
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In: IEEE International Test Conference (TC), 01.12.1996, p. 225-231.
Research output: Contribution to journal › Conference article › Research › peer review
}
TY - JOUR
T1 - Asynchronous scan path concept for micropipelines using the bundled data convention
AU - Schöber, Volker
AU - Kiel, Thomas
PY - 1996/12/1
Y1 - 1996/12/1
N2 - This paper presents a Scan path design to ease the controllability and observability of Self-timed logic. The Scan path registers operate in asynchronous mode during operation and test. Therefore, no synchronous test clock is necessary during the test mode. New test control modules provide the control sequences to switch between the parallel data path and the serial Scan path. In addition to the data path, the control path and the bundled data interface is integrated into the test concept. The new Scan path register has been developed with low area overhead and a small additional delay in the critical data path. An example is used to verify this DFT modules for the data and the control path. It demonstrates the functionality during test and operational made and the compact realization of the asynchronous scan register.
AB - This paper presents a Scan path design to ease the controllability and observability of Self-timed logic. The Scan path registers operate in asynchronous mode during operation and test. Therefore, no synchronous test clock is necessary during the test mode. New test control modules provide the control sequences to switch between the parallel data path and the serial Scan path. In addition to the data path, the control path and the bundled data interface is integrated into the test concept. The new Scan path register has been developed with low area overhead and a small additional delay in the critical data path. An example is used to verify this DFT modules for the data and the control path. It demonstrates the functionality during test and operational made and the compact realization of the asynchronous scan register.
KW - Asynchronous Design, Testability, Production Test, Scan Design
UR - http://www.scopus.com/inward/record.url?scp=0030398942&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:0030398942
SP - 225
EP - 231
JO - IEEE International Test Conference (TC)
JF - IEEE International Test Conference (TC)
SN - 1089-3539
T2 - 1996 IEEE International Test Conference (ITC)
Y2 - 20 October 1996 through 25 October 1996
ER -