Details
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the International Conference on Application Specific Array Processors, ASAP 1991 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 25-39 |
| Number of pages | 15 |
| ISBN (electronic) | 0818692375, 9780818692376 |
| Publication status | Published - 2 Sept 1991 |
| Event | 1991 International Conference on Application Specific Array Processors, ASAP 1991 - Barcelona, Spain Duration: 2 Sept 1991 → 4 Sept 1991 |
Abstract
An advanced defect tolerant systolic array implementation of the 2D convolution algorithm for real-time image processing applications is presented. The chip contrasts with available convolution chips by the maximum kernel size of 256 taps, the ability to convolve one video signal with up to four independent coefficient masks, support of adaptive filtering, on-chip delay lines and implemented special processing of frames borders. Defect tolerance e.g. reconfiguration is implemented in order to enhance yield and reliability especially for future large area implementations.
ASJC Scopus subject areas
- Engineering(all)
- Electrical and Electronic Engineering
- Computer Science(all)
- Signal Processing
- Engineering(all)
- Control and Systems Engineering
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Proceedings of the International Conference on Application Specific Array Processors, ASAP 1991. Institute of Electrical and Electronics Engineers Inc., 1991. p. 25-39 238895.
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - A defect tolerant systolic array implementation for real time image processing
AU - Hecht, V.
AU - Rönner, K.
AU - Pirsch, P.
N1 - Publisher Copyright: ©1991 IEEE.
PY - 1991/9/2
Y1 - 1991/9/2
N2 - An advanced defect tolerant systolic array implementation of the 2D convolution algorithm for real-time image processing applications is presented. The chip contrasts with available convolution chips by the maximum kernel size of 256 taps, the ability to convolve one video signal with up to four independent coefficient masks, support of adaptive filtering, on-chip delay lines and implemented special processing of frames borders. Defect tolerance e.g. reconfiguration is implemented in order to enhance yield and reliability especially for future large area implementations.
AB - An advanced defect tolerant systolic array implementation of the 2D convolution algorithm for real-time image processing applications is presented. The chip contrasts with available convolution chips by the maximum kernel size of 256 taps, the ability to convolve one video signal with up to four independent coefficient masks, support of adaptive filtering, on-chip delay lines and implemented special processing of frames borders. Defect tolerance e.g. reconfiguration is implemented in order to enhance yield and reliability especially for future large area implementations.
UR - http://www.scopus.com/inward/record.url?scp=84936505716&partnerID=8YFLogxK
U2 - 10.1109/ASAP.1991.238895
DO - 10.1109/ASAP.1991.238895
M3 - Conference contribution
AN - SCOPUS:84936505716
SP - 25
EP - 39
BT - Proceedings of the International Conference on Application Specific Array Processors, ASAP 1991
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 1991 International Conference on Application Specific Array Processors, ASAP 1991
Y2 - 2 September 1991 through 4 September 1991
ER -