Details
| Original language | English |
|---|---|
| Title of host publication | 2025 IEEE International Solid-State Circuits Conference, ISSCC 2025 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (electronic) | 9798331541019 |
| ISBN (print) | 979-8-3315-4102-6 |
| Publication status | Published - 16 Feb 2025 |
| Event | 72nd IEEE International Solid-State Circuits Conference, ISSCC 2025 - San Francisco, United States Duration: 16 Feb 2025 → 20 Feb 2025 |
Publication series
| Name | Digest of Technical Papers - IEEE International Solid-State Circuits Conference |
|---|---|
| ISSN (Print) | 0193-6530 |
| ISSN (electronic) | 2376-8606 |
Abstract
Trapped ions (TI) are one of the leading platforms for the realization of a universal quantum computer (QC). They feature several advantages compared to competing technologies. Key benefits of TI qubits utilizing hyperfine transitions are the long achievable coherence time T2 of up to hours and the almost infinite excited state lifetime T1 [1]. The error rate of single-qubit operations is already in the 10-6 range [2], while the error rate of entangled two-qubit gates approaches the fault tolerance error-correction threshold of 10-4 [3,4]. The combined state preparation and measurement fidelity depends on the ion species and is usually above 99.5%. Ion traps can comfortably work at moderate cryogenic temperatures around 4 K, and even room temperature (RT) operation has been demonstrated [4]. The quantum-charge-coupled-device (QCCD) [5,6] architecture allows scalable ion trapping and shuttling, thus enabling all-to-all qubit interconnection.
ASJC Scopus subject areas
- Materials Science(all)
- Electronic, Optical and Magnetic Materials
- Engineering(all)
- Electrical and Electronic Engineering
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2025 IEEE International Solid-State Circuits Conference, ISSCC 2025. Institute of Electrical and Electronics Engineers Inc., 2025. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - A Cryo-BiCMOS Controller for 9Be+-Trapped-Ion-Based Quantum Computers
AU - Toth, Peter
AU - Shine, Paul E.
AU - Halama, Sebastian
AU - Kudabay, Yerzhan
AU - Yamashit, Kaoru
AU - Ishikuro, Hiroki
AU - Ospelkaus, Christian
AU - Issakov, Vadim
N1 - Publisher Copyright: © 2025 IEEE.
PY - 2025/2/16
Y1 - 2025/2/16
N2 - Trapped ions (TI) are one of the leading platforms for the realization of a universal quantum computer (QC). They feature several advantages compared to competing technologies. Key benefits of TI qubits utilizing hyperfine transitions are the long achievable coherence time T2 of up to hours and the almost infinite excited state lifetime T1 [1]. The error rate of single-qubit operations is already in the 10-6 range [2], while the error rate of entangled two-qubit gates approaches the fault tolerance error-correction threshold of 10-4 [3,4]. The combined state preparation and measurement fidelity depends on the ion species and is usually above 99.5%. Ion traps can comfortably work at moderate cryogenic temperatures around 4 K, and even room temperature (RT) operation has been demonstrated [4]. The quantum-charge-coupled-device (QCCD) [5,6] architecture allows scalable ion trapping and shuttling, thus enabling all-to-all qubit interconnection.
AB - Trapped ions (TI) are one of the leading platforms for the realization of a universal quantum computer (QC). They feature several advantages compared to competing technologies. Key benefits of TI qubits utilizing hyperfine transitions are the long achievable coherence time T2 of up to hours and the almost infinite excited state lifetime T1 [1]. The error rate of single-qubit operations is already in the 10-6 range [2], while the error rate of entangled two-qubit gates approaches the fault tolerance error-correction threshold of 10-4 [3,4]. The combined state preparation and measurement fidelity depends on the ion species and is usually above 99.5%. Ion traps can comfortably work at moderate cryogenic temperatures around 4 K, and even room temperature (RT) operation has been demonstrated [4]. The quantum-charge-coupled-device (QCCD) [5,6] architecture allows scalable ion trapping and shuttling, thus enabling all-to-all qubit interconnection.
UR - http://www.scopus.com/inward/record.url?scp=105000830563&partnerID=8YFLogxK
U2 - 10.1109/ISSCC49661.2025.10904696
DO - 10.1109/ISSCC49661.2025.10904696
M3 - Conference contribution
AN - SCOPUS:105000830563
SN - 979-8-3315-4102-6
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
BT - 2025 IEEE International Solid-State Circuits Conference, ISSCC 2025
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 72nd IEEE International Solid-State Circuits Conference, ISSCC 2025
Y2 - 16 February 2025 through 20 February 2025
ER -