Details
| Originalsprache | Englisch |
|---|---|
| Aufsatznummer | 114118 |
| Fachzeitschrift | Microelectronics reliability |
| Jahrgang | 120 |
| Frühes Online-Datum | 17 Apr. 2021 |
| Publikationsstatus | Veröffentlicht - Mai 2021 |
Abstract
Quad-Flat-No-Lead (QFN) packages are electric components that are producing a substantial amount of heat during operation due to significant power loss. Resulting elevated temperatures can lead to critical damage of the chip and the package, which could cause a loss of functionality. Therefore, controlling the maximum temperature within the package is crucial. Using thermal vias embedded in the PCB underneath the QFN is a common concept to support the heat flow. In this paper a simulation approach is presented using 3D Finite-Element-Modelling to identify the impact of influencing parameters on the temperature distribution within the package. Therefore, the build-up of the model is explained and applied material properties are given. Results for the determined temperature distribution for a reference parameter set are presented. Geometrical parameters like the thickness and the area size of the thermal pads and the copper layers are varied. Furthermore, the via count and distribution has been changed and additional inner layers have been added in order to act as a heat sink. The impact of these variations on the resulting component temperature will be discussed in the analysis part. The paper will round up with a discussion of simulation results and an outlook for future work.
ASJC Scopus Sachgebiete
- Werkstoffwissenschaften (insg.)
- Elektronische, optische und magnetische Materialien
- Physik und Astronomie (insg.)
- Atom- und Molekularphysik sowie Optik
- Physik und Astronomie (insg.)
- Physik der kondensierten Materie
- Ingenieurwesen (insg.)
- Sicherheit, Risiko, Zuverlässigkeit und Qualität
- Werkstoffwissenschaften (insg.)
- Oberflächen, Beschichtungen und Folien
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
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in: Microelectronics reliability, Jahrgang 120, 114118, 05.2021.
Publikation: Beitrag in Fachzeitschrift › Artikel › Forschung › Peer-Review
}
TY - JOUR
T1 - Thermal analysis of the design parameters of a QFN package soldered on a PCB using a simulation approach
AU - Hollstein, K.
AU - Yang, X.
AU - Weide-Zaage, K.
PY - 2021/5
Y1 - 2021/5
N2 - Quad-Flat-No-Lead (QFN) packages are electric components that are producing a substantial amount of heat during operation due to significant power loss. Resulting elevated temperatures can lead to critical damage of the chip and the package, which could cause a loss of functionality. Therefore, controlling the maximum temperature within the package is crucial. Using thermal vias embedded in the PCB underneath the QFN is a common concept to support the heat flow. In this paper a simulation approach is presented using 3D Finite-Element-Modelling to identify the impact of influencing parameters on the temperature distribution within the package. Therefore, the build-up of the model is explained and applied material properties are given. Results for the determined temperature distribution for a reference parameter set are presented. Geometrical parameters like the thickness and the area size of the thermal pads and the copper layers are varied. Furthermore, the via count and distribution has been changed and additional inner layers have been added in order to act as a heat sink. The impact of these variations on the resulting component temperature will be discussed in the analysis part. The paper will round up with a discussion of simulation results and an outlook for future work.
AB - Quad-Flat-No-Lead (QFN) packages are electric components that are producing a substantial amount of heat during operation due to significant power loss. Resulting elevated temperatures can lead to critical damage of the chip and the package, which could cause a loss of functionality. Therefore, controlling the maximum temperature within the package is crucial. Using thermal vias embedded in the PCB underneath the QFN is a common concept to support the heat flow. In this paper a simulation approach is presented using 3D Finite-Element-Modelling to identify the impact of influencing parameters on the temperature distribution within the package. Therefore, the build-up of the model is explained and applied material properties are given. Results for the determined temperature distribution for a reference parameter set are presented. Geometrical parameters like the thickness and the area size of the thermal pads and the copper layers are varied. Furthermore, the via count and distribution has been changed and additional inner layers have been added in order to act as a heat sink. The impact of these variations on the resulting component temperature will be discussed in the analysis part. The paper will round up with a discussion of simulation results and an outlook for future work.
KW - PCB design
KW - PCB thermal management
KW - QFN
KW - Quad-Flat-No-Lead
KW - Thermal vias
UR - http://www.scopus.com/inward/record.url?scp=85104282903&partnerID=8YFLogxK
U2 - 10.1016/j.microrel.2021.114118
DO - 10.1016/j.microrel.2021.114118
M3 - Article
AN - SCOPUS:85104282903
VL - 120
JO - Microelectronics reliability
JF - Microelectronics reliability
SN - 0026-2714
M1 - 114118
ER -