SmartHeaP: A High-level Programmable, Low Power, and Mixed-Signal Hearing Aid SoC in 22nm FD-SOI

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OriginalspracheEnglisch
Titel des SammelwerksESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)
Seiten265-268
Seitenumfang4
ISBN (elektronisch)978-1-6654-8494-7
PublikationsstatusVeröffentlicht - 2022

Abstract

To handle the advances in hearing aid algorithms, the need for high-level programmable but low-power hardware architectures arises. Therefore, this paper presents the Smart Hearing Aid Processor (SmartHeaP), a mixed-signal system on chip (SoC) fabricated in 22 nm fully-depleted silicon-on-insulator (FD-SOI) with an adaptive body biasing (ABB) unit and a total die size of 7.36 mm² . The proposed SoC consists of two application-specific instruction set processor (ASIP) architectures: firstly, a Cadence Tensilica Fusion G6 instruction set architecture, extended with custom instructions for audio processing, and secondly, a Cadence Tensilica LX7 for wireless interfacing, e.g., Bluetooth Low Energy. Furthermore, an analog front-end and digital audio interfaces are added. The large local memory of 2 MB and a high-level software environment enables memory-intensive algorithms to be deployed quickly. Typical hearing aid algorithms in a real-time setup are used to evaluate the power consumption of the SoC at different operating frequencies. At 50 MHz, a mean power consumption of less than 2.2 mW was measured, resulting in an efficiency of 34.8 µW/MHz.

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SmartHeaP: A High-level Programmable, Low Power, and Mixed-Signal Hearing Aid SoC in 22nm FD-SOI. / Karrenbauer, Jens Christian; Klein, Simon Christian; Schönewald, Sven Johannes et al.
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC). 2022. S. 265-268.

Publikation: Beitrag in Buch/Bericht/Sammelwerk/KonferenzbandAufsatz in KonferenzbandForschungPeer-Review

Karrenbauer, JC, Klein, SC, Schönewald, SJ, Gerlach, LK, Blawat, M, Benndorf, J & Blume, HC 2022, SmartHeaP: A High-level Programmable, Low Power, and Mixed-Signal Hearing Aid SoC in 22nm FD-SOI. in ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC). S. 265-268. https://doi.org/10.1109/ESSCIRC55480.2022.9911325
Karrenbauer, J. C., Klein, S. C., Schönewald, S. J., Gerlach, L. K., Blawat, M., Benndorf, J., & Blume, H. C. (2022). SmartHeaP: A High-level Programmable, Low Power, and Mixed-Signal Hearing Aid SoC in 22nm FD-SOI. In ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) (S. 265-268) https://doi.org/10.1109/ESSCIRC55480.2022.9911325
Karrenbauer JC, Klein SC, Schönewald SJ, Gerlach LK, Blawat M, Benndorf J et al. SmartHeaP: A High-level Programmable, Low Power, and Mixed-Signal Hearing Aid SoC in 22nm FD-SOI. in ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC). 2022. S. 265-268 doi: 10.1109/ESSCIRC55480.2022.9911325
Karrenbauer, Jens Christian ; Klein, Simon Christian ; Schönewald, Sven Johannes et al. / SmartHeaP : A High-level Programmable, Low Power, and Mixed-Signal Hearing Aid SoC in 22nm FD-SOI. ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC). 2022. S. 265-268
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title = "SmartHeaP: A High-level Programmable, Low Power, and Mixed-Signal Hearing Aid SoC in 22nm FD-SOI",
abstract = "To handle the advances in hearing aid algorithms, the need for high-level programmable but low-power hardware architectures arises. Therefore, this paper presents the Smart Hearing Aid Processor (SmartHeaP), a mixed-signal system on chip (SoC) fabricated in 22 nm fully-depleted silicon-on-insulator (FD-SOI) with an adaptive body biasing (ABB) unit and a total die size of 7.36 mm² . The proposed SoC consists of two application-specific instruction set processor (ASIP) architectures: firstly, a Cadence Tensilica Fusion G6 instruction set architecture, extended with custom instructions for audio processing, and secondly, a Cadence Tensilica LX7 for wireless interfacing, e.g., Bluetooth Low Energy. Furthermore, an analog front-end and digital audio interfaces are added. The large local memory of 2 MB and a high-level software environment enables memory-intensive algorithms to be deployed quickly. Typical hearing aid algorithms in a real-time setup are used to evaluate the power consumption of the SoC at different operating frequencies. At 50 MHz, a mean power consumption of less than 2.2 mW was measured, resulting in an efficiency of 34.8 µW/MHz.",
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T2 - A High-level Programmable, Low Power, and Mixed-Signal Hearing Aid SoC in 22nm FD-SOI

AU - Karrenbauer, Jens Christian

AU - Klein, Simon Christian

AU - Schönewald, Sven Johannes

AU - Gerlach, Lukas Konrad

AU - Blawat, Meinolf

AU - Benndorf, Jens

AU - Blume, Holger Christoph

N1 - Funding Information: This work was funded by the Federal Ministry of Education and Research of Germany (BMBF) - project number 16ES0759. We also like to thank the partners for the excellent cooperation, especially Hörzentrum Oldenburg for the algorithmic support, Cadence Design Systems for providing the Tensilica and other IPs and support related EDA tools, SoC and architecture design methodology, and GlobalFoundries for the fabricated 22 FDX silicon.

PY - 2022

Y1 - 2022

N2 - To handle the advances in hearing aid algorithms, the need for high-level programmable but low-power hardware architectures arises. Therefore, this paper presents the Smart Hearing Aid Processor (SmartHeaP), a mixed-signal system on chip (SoC) fabricated in 22 nm fully-depleted silicon-on-insulator (FD-SOI) with an adaptive body biasing (ABB) unit and a total die size of 7.36 mm² . The proposed SoC consists of two application-specific instruction set processor (ASIP) architectures: firstly, a Cadence Tensilica Fusion G6 instruction set architecture, extended with custom instructions for audio processing, and secondly, a Cadence Tensilica LX7 for wireless interfacing, e.g., Bluetooth Low Energy. Furthermore, an analog front-end and digital audio interfaces are added. The large local memory of 2 MB and a high-level software environment enables memory-intensive algorithms to be deployed quickly. Typical hearing aid algorithms in a real-time setup are used to evaluate the power consumption of the SoC at different operating frequencies. At 50 MHz, a mean power consumption of less than 2.2 mW was measured, resulting in an efficiency of 34.8 µW/MHz.

AB - To handle the advances in hearing aid algorithms, the need for high-level programmable but low-power hardware architectures arises. Therefore, this paper presents the Smart Hearing Aid Processor (SmartHeaP), a mixed-signal system on chip (SoC) fabricated in 22 nm fully-depleted silicon-on-insulator (FD-SOI) with an adaptive body biasing (ABB) unit and a total die size of 7.36 mm² . The proposed SoC consists of two application-specific instruction set processor (ASIP) architectures: firstly, a Cadence Tensilica Fusion G6 instruction set architecture, extended with custom instructions for audio processing, and secondly, a Cadence Tensilica LX7 for wireless interfacing, e.g., Bluetooth Low Energy. Furthermore, an analog front-end and digital audio interfaces are added. The large local memory of 2 MB and a high-level software environment enables memory-intensive algorithms to be deployed quickly. Typical hearing aid algorithms in a real-time setup are used to evaluate the power consumption of the SoC at different operating frequencies. At 50 MHz, a mean power consumption of less than 2.2 mW was measured, resulting in an efficiency of 34.8 µW/MHz.

KW - 22nm FD-SOI

KW - ABB

KW - ASIC

KW - ASIP

KW - Tensilica

KW - hearing aid

KW - instruction extension

KW - low power

KW - system on chip (SoC)

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U2 - 10.1109/ESSCIRC55480.2022.9911325

DO - 10.1109/ESSCIRC55480.2022.9911325

M3 - Conference contribution

SN - 978-1-6654-8493-0

SN - 978-1-6654-8495-4

SP - 265

EP - 268

BT - ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)

ER -

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