Optimization of chip design processes using task graphs

Publikation: Beitrag in Buch/Bericht/Sammelwerk/KonferenzbandAufsatz in KonferenzbandForschungPeer-Review

Autorschaft

  • Neele Hinrichs
  • Markus Olbrich
  • Erich Barke
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Details

OriginalspracheEnglisch
Titel des SammelwerksICSTE 2010 - 2010 2nd International Conference on Software Technology and Engineering, Proceedings
SeitenV1116-V1120
PublikationsstatusVeröffentlicht - 2010
Veranstaltung2010 2nd International Conference on Software Technology and Engineering, ICSTE 2010 - San Juan, PR, USA / Vereinigte Staaten
Dauer: 3 Okt. 20105 Okt. 2010

Publikationsreihe

NameICSTE 2010 - 2010 2nd International Conference on Software Technology and Engineering, Proceedings
Band1

Abstract

The semiconductor industry is characterized by highly progressive and complex products. Fast technological change and improvement lead to increasing complexity of the design process which makes project scheduling and resource management more and more challenging. The variety of influencing factors makes it complicated to predict the main parameters affecting the project success. In our approach a task graph is generated automatically from design process data to clarify the dependencies between the activities. In a second step, the process and the allocation of resources are optimized and evaluated regarding main objectives as time and cost.

ASJC Scopus Sachgebiete

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Optimization of chip design processes using task graphs. / Hinrichs, Neele; Olbrich, Markus; Barke, Erich.
ICSTE 2010 - 2010 2nd International Conference on Software Technology and Engineering, Proceedings. 2010. S. V1116-V1120 5608900 (ICSTE 2010 - 2010 2nd International Conference on Software Technology and Engineering, Proceedings; Band 1).

Publikation: Beitrag in Buch/Bericht/Sammelwerk/KonferenzbandAufsatz in KonferenzbandForschungPeer-Review

Hinrichs, N, Olbrich, M & Barke, E 2010, Optimization of chip design processes using task graphs. in ICSTE 2010 - 2010 2nd International Conference on Software Technology and Engineering, Proceedings., 5608900, ICSTE 2010 - 2010 2nd International Conference on Software Technology and Engineering, Proceedings, Bd. 1, S. V1116-V1120, 2010 2nd International Conference on Software Technology and Engineering, ICSTE 2010, San Juan, PR, USA / Vereinigte Staaten, 3 Okt. 2010. https://doi.org/10.1109/ICSTE.2010.5608900
Hinrichs, N., Olbrich, M., & Barke, E. (2010). Optimization of chip design processes using task graphs. In ICSTE 2010 - 2010 2nd International Conference on Software Technology and Engineering, Proceedings (S. V1116-V1120). Artikel 5608900 (ICSTE 2010 - 2010 2nd International Conference on Software Technology and Engineering, Proceedings; Band 1). https://doi.org/10.1109/ICSTE.2010.5608900
Hinrichs N, Olbrich M, Barke E. Optimization of chip design processes using task graphs. in ICSTE 2010 - 2010 2nd International Conference on Software Technology and Engineering, Proceedings. 2010. S. V1116-V1120. 5608900. (ICSTE 2010 - 2010 2nd International Conference on Software Technology and Engineering, Proceedings). doi: 10.1109/ICSTE.2010.5608900
Hinrichs, Neele ; Olbrich, Markus ; Barke, Erich. / Optimization of chip design processes using task graphs. ICSTE 2010 - 2010 2nd International Conference on Software Technology and Engineering, Proceedings. 2010. S. V1116-V1120 (ICSTE 2010 - 2010 2nd International Conference on Software Technology and Engineering, Proceedings).
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