Details
| Originalsprache | Englisch |
|---|---|
| Titel des Sammelwerks | Proceedings - 2024 IEEE 35th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2024 |
| Herausgeber (Verlag) | Institute of Electrical and Electronics Engineers Inc. |
| Seiten | 1-2 |
| Seitenumfang | 2 |
| ISBN (elektronisch) | 9798350349634 |
| ISBN (Print) | 979-8-3503-4964-1 |
| Publikationsstatus | Veröffentlicht - 2024 |
| Veranstaltung | 35th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2024 - Hongkong, Hongkong Dauer: 24 Juli 2024 → 26 Juli 2024 |
Publikationsreihe
| Name | Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors |
|---|---|
| ISSN (Print) | 2160-0511 |
| ISSN (elektronisch) | 2160-052X |
Abstract
Modern embedded systems must be designed carefully to cope with the complexity and real-time requirements of modern AI (Artificial Intelligence) driven automotive applications, such as Advanced Driver-Assistance Systems (ADAS). Despite increasing complexity, the time to market is decreasing. In this work, a SystemC-based Virtual Prototype of a neural network processing platform is exploited to bypass the limitations of standalone instruction set simulators (ISS) and FPGA prototyping. The processing platform under test is based on a novel massive parallel vector processor architecture coupled with a RISC- V control core that runs widely used convolutional neural networks (CNNs) for object detection. The paper discusses the variations and appropriateness of the three prototyping methods outlined, demonstrating how the Virtual Prototype can address the aforementioned constraints, resulting in a 2.07x increase in accuracy, 16x greater configurations, and more profound insights into the system compared to standalone and FPGA prototyping.
ASJC Scopus Sachgebiete
- Informatik (insg.)
- Hardware und Architektur
- Informatik (insg.)
- Computernetzwerke und -kommunikation
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- BibTex
- RIS
Proceedings - 2024 IEEE 35th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2024. Institute of Electrical and Electronics Engineers Inc., 2024. S. 1-2 (Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors).
Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review
}
TY - GEN
T1 - Multi-Level Prototyping of a Vertical Vector AI Processing System
AU - Kautz, Frederik
AU - Gesper, Sven
AU - Thieu, Gia Bao
AU - Bluethgen, Hans Martin
AU - Blume, Holger
AU - Paya-Vaya, Guillermo
N1 - Publisher Copyright: © 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - Modern embedded systems must be designed carefully to cope with the complexity and real-time requirements of modern AI (Artificial Intelligence) driven automotive applications, such as Advanced Driver-Assistance Systems (ADAS). Despite increasing complexity, the time to market is decreasing. In this work, a SystemC-based Virtual Prototype of a neural network processing platform is exploited to bypass the limitations of standalone instruction set simulators (ISS) and FPGA prototyping. The processing platform under test is based on a novel massive parallel vector processor architecture coupled with a RISC- V control core that runs widely used convolutional neural networks (CNNs) for object detection. The paper discusses the variations and appropriateness of the three prototyping methods outlined, demonstrating how the Virtual Prototype can address the aforementioned constraints, resulting in a 2.07x increase in accuracy, 16x greater configurations, and more profound insights into the system compared to standalone and FPGA prototyping.
AB - Modern embedded systems must be designed carefully to cope with the complexity and real-time requirements of modern AI (Artificial Intelligence) driven automotive applications, such as Advanced Driver-Assistance Systems (ADAS). Despite increasing complexity, the time to market is decreasing. In this work, a SystemC-based Virtual Prototype of a neural network processing platform is exploited to bypass the limitations of standalone instruction set simulators (ISS) and FPGA prototyping. The processing platform under test is based on a novel massive parallel vector processor architecture coupled with a RISC- V control core that runs widely used convolutional neural networks (CNNs) for object detection. The paper discusses the variations and appropriateness of the three prototyping methods outlined, demonstrating how the Virtual Prototype can address the aforementioned constraints, resulting in a 2.07x increase in accuracy, 16x greater configurations, and more profound insights into the system compared to standalone and FPGA prototyping.
KW - AI
KW - Automotive
KW - CNN
KW - Design Space Exploration
KW - Instruction Set Simulator
KW - RISC-V
KW - Virtual Prototype
UR - http://www.scopus.com/inward/record.url?scp=85203105689&partnerID=8YFLogxK
U2 - 10.1109/asap61560.2024.00011
DO - 10.1109/asap61560.2024.00011
M3 - Conference contribution
AN - SCOPUS:85203105689
SN - 979-8-3503-4964-1
T3 - Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
SP - 1
EP - 2
BT - Proceedings - 2024 IEEE 35th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2024
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 35th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2024
Y2 - 24 July 2024 through 26 July 2024
ER -