Details
Originalsprache | Englisch |
---|---|
Titel des Sammelwerks | 2024 Panhellenic Conference on Electronics & Telecommunications (PACET) |
Seiten | 1-6 |
Seitenumfang | 6 |
ISBN (elektronisch) | 979-8-3503-1884-5 |
Publikationsstatus | Veröffentlicht - 2024 |
Publikationsreihe
Name | Panhellenic Conference on Electronics & Telecommunications (PACET) |
---|---|
Herausgeber (Verlag) | IEEE |
Abstract
ASJC Scopus Sachgebiete
- Informatik (insg.)
- Signalverarbeitung
- Energie (insg.)
- Energieanlagenbau und Kraftwerkstechnik
- Physik und Astronomie (insg.)
- Instrumentierung
- Medizin (insg.)
- Gesundheitsinformatik
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
- Informatik (insg.)
- Computernetzwerke und -kommunikation
Zitieren
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- BibTex
- RIS
2024 Panhellenic Conference on Electronics & Telecommunications (PACET). 2024. S. 1-6 (Panhellenic Conference on Electronics & Telecommunications (PACET)).
Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review
}
TY - GEN
T1 - Improving Clock Frequencies in ASIC Designs through Semi-Automatic Register Placement and Advanced Retiming
AU - Hawich, Malte
AU - Klein, Simon Christian
AU - Stuckenberg, Tobias
AU - Blume, Holger Christoph
PY - 2024
Y1 - 2024
N2 - In hardware design, pipelining is a key technique for achieving high clock frequencies, typically by placing registers along the critical path of a design to minimize its length. As the complexity of hardware designs has increased, the potential for deeper pipeline configurations has emerged. Modern synthesis tools utilize register retiming, which adjusts register locations to balance the critical paths between them. Designers have several choices when tackling such challenging designs: place registers at the end of the design in conjunction with the synthesis tool’s retiming, optimize register placement manually to balance path distances, or combine both strategies. The pursuit of peak clock frequencies often requires the labor-intensive manual approach.In this paper, we present an innovative method that semi- automatically places registers along a design’s critical path as an initial seed that is subsequently used for retiming. Our case study, which analyzes several state-of-the-art regular and irregular multiplier designs synthesised for an ASIC technology for challenging environments, shows that this enhanced retiming increases the maximum achievable clock frequencies by up to 51 % over the traditional register appending method. Compared to the manual approach, the performance is similar, but the manual effort is greatly reduced.
AB - In hardware design, pipelining is a key technique for achieving high clock frequencies, typically by placing registers along the critical path of a design to minimize its length. As the complexity of hardware designs has increased, the potential for deeper pipeline configurations has emerged. Modern synthesis tools utilize register retiming, which adjusts register locations to balance the critical paths between them. Designers have several choices when tackling such challenging designs: place registers at the end of the design in conjunction with the synthesis tool’s retiming, optimize register placement manually to balance path distances, or combine both strategies. The pursuit of peak clock frequencies often requires the labor-intensive manual approach.In this paper, we present an innovative method that semi- automatically places registers along a design’s critical path as an initial seed that is subsequently used for retiming. Our case study, which analyzes several state-of-the-art regular and irregular multiplier designs synthesised for an ASIC technology for challenging environments, shows that this enhanced retiming increases the maximum achievable clock frequencies by up to 51 % over the traditional register appending method. Compared to the manual approach, the performance is similar, but the manual effort is greatly reduced.
KW - ASIC
KW - Hardware Design
KW - Harsh Environment
KW - High Performance
KW - Multiplier
KW - Pipeline
KW - Register Placement
KW - Retiming
UR - http://www.scopus.com/inward/record.url?scp=85191655292&partnerID=8YFLogxK
U2 - 10.1109/PACET60398.2024.10497079
DO - 10.1109/PACET60398.2024.10497079
M3 - Conference contribution
SN - 979-8-3503-1885-2
T3 - Panhellenic Conference on Electronics & Telecommunications (PACET)
SP - 1
EP - 6
BT - 2024 Panhellenic Conference on Electronics & Telecommunications (PACET)
ER -