Details
| Originalsprache | Englisch |
|---|---|
| Titel des Sammelwerks | 2025 Design, Automation and Test in Europe Conference, DATE 2025 - Proceedings |
| Herausgeber (Verlag) | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (elektronisch) | 9783982674100 |
| ISBN (Print) | 979-8-3315-3464-6 |
| Publikationsstatus | Veröffentlicht - 31 März 2025 |
| Veranstaltung | 2025 Design, Automation and Test in Europe Conference, DATE 2025 - Lyon, Frankreich Dauer: 31 März 2025 → 2 Apr. 2025 |
Publikationsreihe
| Name | Proceedings -Design, Automation and Test in Europe, DATE |
|---|---|
| ISSN (Print) | 1530-1591 |
Abstract
Training and running inference of large neural networks comes with excessive cost and power consumption. Thus, realizing these networks as analog circuits is an energy-and areaefficient alternative. However, analog neural networks suffer from inherent deviations within their circuits, requiring extensive testing for their correct behavior under these deviations. Unfortunately, tests based on Monte Carlo simulations are extremely time- and resource-intensive. We present an alternative approach to proving the correctness of the neural network using formal neural network verification techniques and developing a modeling methodology for these analog neural circuits. Our experimental results compare two methods based on reachability analysis showing their effectiveness by reducing the test time from days to milliseconds. Thus, they offer a faster, more scalable solution for verifying the correctness of analog neural circuits.
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2025 Design, Automation and Test in Europe Conference, DATE 2025 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2025. (Proceedings -Design, Automation and Test in Europe, DATE).
Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review
, Lyon, Frankreich, 31 März 2025. https://doi.org/10.23919/DATE64628.2025.10992891
}
TY - GEN
T1 - Formally Verifying Analog Neural Networks with Device Mismatch Variations
AU - Abu-Haeyeh, Yasmine
AU - Bartelsmeier, Thomas
AU - Ladner, Tobias
AU - Althoff, Matthias
AU - Hedrich, Lars
AU - Olbrich, Markus
N1 - Publisher Copyright: © 2025 EDAA.
PY - 2025/3/31
Y1 - 2025/3/31
N2 - Training and running inference of large neural networks comes with excessive cost and power consumption. Thus, realizing these networks as analog circuits is an energy-and areaefficient alternative. However, analog neural networks suffer from inherent deviations within their circuits, requiring extensive testing for their correct behavior under these deviations. Unfortunately, tests based on Monte Carlo simulations are extremely time- and resource-intensive. We present an alternative approach to proving the correctness of the neural network using formal neural network verification techniques and developing a modeling methodology for these analog neural circuits. Our experimental results compare two methods based on reachability analysis showing their effectiveness by reducing the test time from days to milliseconds. Thus, they offer a faster, more scalable solution for verifying the correctness of analog neural circuits.
AB - Training and running inference of large neural networks comes with excessive cost and power consumption. Thus, realizing these networks as analog circuits is an energy-and areaefficient alternative. However, analog neural networks suffer from inherent deviations within their circuits, requiring extensive testing for their correct behavior under these deviations. Unfortunately, tests based on Monte Carlo simulations are extremely time- and resource-intensive. We present an alternative approach to proving the correctness of the neural network using formal neural network verification techniques and developing a modeling methodology for these analog neural circuits. Our experimental results compare two methods based on reachability analysis showing their effectiveness by reducing the test time from days to milliseconds. Thus, they offer a faster, more scalable solution for verifying the correctness of analog neural circuits.
KW - AI hardware
KW - Analog neural networks
KW - energy-efficient computing
KW - formal verification
KW - set-based computing
UR - http://www.scopus.com/inward/record.url?scp=105006897263&partnerID=8YFLogxK
U2 - 10.23919/DATE64628.2025.10992891
DO - 10.23919/DATE64628.2025.10992891
M3 - Conference contribution
AN - SCOPUS:105006897263
SN - 979-8-3315-3464-6
T3 - Proceedings -Design, Automation and Test in Europe, DATE
BT - 2025 Design, Automation and Test in Europe Conference, DATE 2025 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2025 Design, Automation and Test in Europe Conference, DATE 2025
Y2 - 31 March 2025 through 2 April 2025
ER -