Enhancing RISC-V Processor Performance in Harsh Environments through Data Cache Optimization

Publikation: Beitrag in Buch/Bericht/Sammelwerk/KonferenzbandAufsatz in KonferenzbandForschungPeer-Review

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OriginalspracheEnglisch
Titel des Sammelwerks2024 Panhellenic Conference on Electronics & Telecommunications (PACET)
Seiten1-4
Seitenumfang4
ISBN (elektronisch)979-8-3503-1884-5
PublikationsstatusVeröffentlicht - 2024

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NamePanhellenic Conference on Electronics & Telecommunications (PACET)
Herausgeber (Verlag)IEEE

Abstract

Processor performance is often limited by cache efficiency, a critical aspect in any signal processing task. A RISC-V processor combined with the cache presented in this paper will be part of a deep drilling component manufactured to further automate the entire drilling process. Therefore, signal acquisition, storage, and in-situ processing are required. This paper presents a data cache optimization for a high performance RISC-V processor designed to operate under extreme conditions up to 175°C and 200MPa while maintaining a stable frequency of 180MHz. At the heart of this new design is XFAB’s XT018 technology, a state-of-the-art 180nm SOI technology capable of withstanding the harsh environment in which the core will operate. Memories matching the required clock frequencies will only provide single-port access, adding further challenges to the design. Several caching strategies and implementations are applied and compared to each other in this paper. The design is implemented with a direct connection to the RISC-V core on the one side and a connection to an AXI4 network on the other side. We build this cache that supports multi-port access, with only a single-port SRAM memory at its core. Despite the inherent limitations of single-port SRAMs and the harsh environmental conditions, our design successfully implements a cache system that achieves an impressive hit rate of more than 97%, which is in line with industry standards for consumer grade electronics typically operating at room temperature.

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Enhancing RISC-V Processor Performance in Harsh Environments through Data Cache Optimization. / Frühauf, Jan-Luca; Hawich, Malte; Blume, Holger Christoph.
2024 Panhellenic Conference on Electronics & Telecommunications (PACET). 2024. S. 1-4 (Panhellenic Conference on Electronics & Telecommunications (PACET)).

Publikation: Beitrag in Buch/Bericht/Sammelwerk/KonferenzbandAufsatz in KonferenzbandForschungPeer-Review

Frühauf, J-L, Hawich, M & Blume, HC 2024, Enhancing RISC-V Processor Performance in Harsh Environments through Data Cache Optimization. in 2024 Panhellenic Conference on Electronics & Telecommunications (PACET). Panhellenic Conference on Electronics & Telecommunications (PACET), S. 1-4. https://doi.org/10.1109/PACET60398.2024.10497077
Frühauf, J.-L., Hawich, M., & Blume, H. C. (2024). Enhancing RISC-V Processor Performance in Harsh Environments through Data Cache Optimization. In 2024 Panhellenic Conference on Electronics & Telecommunications (PACET) (S. 1-4). (Panhellenic Conference on Electronics & Telecommunications (PACET)). https://doi.org/10.1109/PACET60398.2024.10497077
Frühauf JL, Hawich M, Blume HC. Enhancing RISC-V Processor Performance in Harsh Environments through Data Cache Optimization. in 2024 Panhellenic Conference on Electronics & Telecommunications (PACET). 2024. S. 1-4. (Panhellenic Conference on Electronics & Telecommunications (PACET)). doi: 10.1109/PACET60398.2024.10497077
Frühauf, Jan-Luca ; Hawich, Malte ; Blume, Holger Christoph. / Enhancing RISC-V Processor Performance in Harsh Environments through Data Cache Optimization. 2024 Panhellenic Conference on Electronics & Telecommunications (PACET). 2024. S. 1-4 (Panhellenic Conference on Electronics & Telecommunications (PACET)).
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