Details
Originalsprache | Englisch |
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Titel des Sammelwerks | 2024 Panhellenic Conference on Electronics & Telecommunications (PACET) |
Seiten | 1-4 |
Seitenumfang | 4 |
ISBN (elektronisch) | 979-8-3503-1884-5 |
Publikationsstatus | Veröffentlicht - 2024 |
Publikationsreihe
Name | Panhellenic Conference on Electronics & Telecommunications (PACET) |
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Herausgeber (Verlag) | IEEE |
Abstract
ASJC Scopus Sachgebiete
- Informatik (insg.)
- Signalverarbeitung
- Energie (insg.)
- Energieanlagenbau und Kraftwerkstechnik
- Informatik (insg.)
- Computernetzwerke und -kommunikation
- Physik und Astronomie (insg.)
- Instrumentierung
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
- Medizin (insg.)
- Gesundheitsinformatik
Zitieren
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- BibTex
- RIS
2024 Panhellenic Conference on Electronics & Telecommunications (PACET). 2024. S. 1-4 (Panhellenic Conference on Electronics & Telecommunications (PACET)).
Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review
}
TY - GEN
T1 - Enhancing RISC-V Processor Performance in Harsh Environments through Data Cache Optimization
AU - Frühauf, Jan-Luca
AU - Hawich, Malte
AU - Blume, Holger Christoph
PY - 2024
Y1 - 2024
N2 - Processor performance is often limited by cache efficiency, a critical aspect in any signal processing task. A RISC-V processor combined with the cache presented in this paper will be part of a deep drilling component manufactured to further automate the entire drilling process. Therefore, signal acquisition, storage, and in-situ processing are required. This paper presents a data cache optimization for a high performance RISC-V processor designed to operate under extreme conditions up to 175°C and 200MPa while maintaining a stable frequency of 180MHz. At the heart of this new design is XFAB’s XT018 technology, a state-of-the-art 180nm SOI technology capable of withstanding the harsh environment in which the core will operate. Memories matching the required clock frequencies will only provide single-port access, adding further challenges to the design. Several caching strategies and implementations are applied and compared to each other in this paper. The design is implemented with a direct connection to the RISC-V core on the one side and a connection to an AXI4 network on the other side. We build this cache that supports multi-port access, with only a single-port SRAM memory at its core. Despite the inherent limitations of single-port SRAMs and the harsh environmental conditions, our design successfully implements a cache system that achieves an impressive hit rate of more than 97%, which is in line with industry standards for consumer grade electronics typically operating at room temperature.
AB - Processor performance is often limited by cache efficiency, a critical aspect in any signal processing task. A RISC-V processor combined with the cache presented in this paper will be part of a deep drilling component manufactured to further automate the entire drilling process. Therefore, signal acquisition, storage, and in-situ processing are required. This paper presents a data cache optimization for a high performance RISC-V processor designed to operate under extreme conditions up to 175°C and 200MPa while maintaining a stable frequency of 180MHz. At the heart of this new design is XFAB’s XT018 technology, a state-of-the-art 180nm SOI technology capable of withstanding the harsh environment in which the core will operate. Memories matching the required clock frequencies will only provide single-port access, adding further challenges to the design. Several caching strategies and implementations are applied and compared to each other in this paper. The design is implemented with a direct connection to the RISC-V core on the one side and a connection to an AXI4 network on the other side. We build this cache that supports multi-port access, with only a single-port SRAM memory at its core. Despite the inherent limitations of single-port SRAMs and the harsh environmental conditions, our design successfully implements a cache system that achieves an impressive hit rate of more than 97%, which is in line with industry standards for consumer grade electronics typically operating at room temperature.
KW - ASIC
KW - RISC-V
KW - cache
KW - data
KW - harsh environment
KW - memory
KW - processor
UR - http://www.scopus.com/inward/record.url?scp=85191652683&partnerID=8YFLogxK
U2 - 10.1109/PACET60398.2024.10497077
DO - 10.1109/PACET60398.2024.10497077
M3 - Conference contribution
SN - 979-8-3503-1885-2
T3 - Panhellenic Conference on Electronics & Telecommunications (PACET)
SP - 1
EP - 4
BT - 2024 Panhellenic Conference on Electronics & Telecommunications (PACET)
ER -