TY - JOUR

T1 - Application of deterministic and stochastic Petri-Nets for performance modeling of NoC architectures

AU - Blume, H.

AU - von Sydow, T.

AU - Becker, D.

AU - Noll, T. G.

PY - 2006/12/21

Y1 - 2006/12/21

N2 - The design of appropriate communication architectures for complex Systems-on-Chip (SoC) is a challenging task. One promising alternative to solve these problems are Networks-on-Chip (NoCs). Recently, the application of deterministic and stochastic Petri-Nets (DSPNs) to model on-chip communication has been proven to be an attractive method to evaluate and explore different communication aspects. In this contribution the modeling of basic NoC communication scenarios featuring different processor cores, network topologies and communication schemes is presented. In order to provide a testbed for the verification of modeling results a state-of-the-art FPGA-platform has been utilized. This platform allows to instantiate a soft-core processor network which can be adapted in terms of communication network topologies and communication schemes. It will be shown that DSPN modeling yields good communication performance prediction results at low modeling effort. Different DSPN modeling aspects in terms of accuracy and computational effort are discussed.

AB - The design of appropriate communication architectures for complex Systems-on-Chip (SoC) is a challenging task. One promising alternative to solve these problems are Networks-on-Chip (NoCs). Recently, the application of deterministic and stochastic Petri-Nets (DSPNs) to model on-chip communication has been proven to be an attractive method to evaluate and explore different communication aspects. In this contribution the modeling of basic NoC communication scenarios featuring different processor cores, network topologies and communication schemes is presented. In order to provide a testbed for the verification of modeling results a state-of-the-art FPGA-platform has been utilized. This platform allows to instantiate a soft-core processor network which can be adapted in terms of communication network topologies and communication schemes. It will be shown that DSPN modeling yields good communication performance prediction results at low modeling effort. Different DSPN modeling aspects in terms of accuracy and computational effort are discussed.

KW - Deterministic and stochastic Petri-Nets

KW - NoC

KW - On-chip communication

KW - Performance Modeling

KW - SoC

UR - http://www.scopus.com/inward/record.url?scp=34248559642&partnerID=8YFLogxK

U2 - 10.1016/j.sysarc.2006.11.001

DO - 10.1016/j.sysarc.2006.11.001

M3 - Article

AN - SCOPUS:34248559642

VL - 53

SP - 466

EP - 476

JO - Journal of Systems Architecture

JF - Journal of Systems Architecture

SN - 1383-7621

IS - 8

ER -