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Optimizing RISC-V Processor Performance with Adaptive Execution Unit Lengths in Harsh Environment Conditio

Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review

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  1. 2024

  2. Published

    High Temperature In-Order RISC-V Processor with Heterogeneous Pipeline and Out-of-Order Write-Back Mechanism

    Hawich, M., Blume, H. C. & Szücs, J., 24 Sept 2024, 2024 Kleinheubach Conference. p. 1-4 4 p.

    Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review