Details
| Original language | English |
|---|---|
| Pages | 1-2 |
| Number of pages | 2 |
| Publication status | Published - 29 Jul 2025 |
| Event | RISC-V Summit 2025 Europe - Cité des sciences et de l'industrie, Paris, France Duration: 12 May 2025 → 15 May 2025 https://riscv-europe.org/summit/2025/ |
Conference
| Conference | RISC-V Summit 2025 Europe |
|---|---|
| Country/Territory | France |
| City | Paris |
| Period | 12 May 2025 → 15 May 2025 |
| Internet address |
Abstract
sustained operation at 180 MHz while withstanding temperatures up to 175°C. Built using a state-of-the-art
180nm silicon-on-insulator (SOI) technology, the processor overcomes the limitations of existing designs, such as
increased leakage currents and reduced carrier mobility in extreme environments. Key innovations include a
deeply pipelined architecture optimized for thermal stability, modular execution pipelines to handle high-latency
operations without stalling, and tightly coupled caches using single-port SRAM with custom wrappers for high
throughput. In contrast to other well known architectures for harsh environments, which usually target radiation
resistance in space, this design is tailored specifically for high-temperature resilience. Extensive testing validated
its performance and reliability.
Keywords
- RISC-V, ASIP, Processor architecture, Hardware architecture
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2025. 1-2 Paper presented at RISC-V Summit 2025 Europe, Paris, France.
Research output: Contribution to conference › Paper › Research › peer review
}
TY - CONF
T1 - High Performance RISC-V Processor for Application in Harsh Environments
AU - Hawich, Malte
AU - Rücker, Malte
AU - Stuckenberg, Tobias
AU - Blume, Holger Christoph
PY - 2025/7/29
Y1 - 2025/7/29
N2 - This work introduces a full custom RISC-V processor specifically targeted for harsh environments capable ofsustained operation at 180 MHz while withstanding temperatures up to 175°C. Built using a state-of-the-art180nm silicon-on-insulator (SOI) technology, the processor overcomes the limitations of existing designs, such asincreased leakage currents and reduced carrier mobility in extreme environments. Key innovations include adeeply pipelined architecture optimized for thermal stability, modular execution pipelines to handle high-latencyoperations without stalling, and tightly coupled caches using single-port SRAM with custom wrappers for highthroughput. In contrast to other well known architectures for harsh environments, which usually target radiationresistance in space, this design is tailored specifically for high-temperature resilience. Extensive testing validatedits performance and reliability.
AB - This work introduces a full custom RISC-V processor specifically targeted for harsh environments capable ofsustained operation at 180 MHz while withstanding temperatures up to 175°C. Built using a state-of-the-art180nm silicon-on-insulator (SOI) technology, the processor overcomes the limitations of existing designs, such asincreased leakage currents and reduced carrier mobility in extreme environments. Key innovations include adeeply pipelined architecture optimized for thermal stability, modular execution pipelines to handle high-latencyoperations without stalling, and tightly coupled caches using single-port SRAM with custom wrappers for highthroughput. In contrast to other well known architectures for harsh environments, which usually target radiationresistance in space, this design is tailored specifically for high-temperature resilience. Extensive testing validatedits performance and reliability.
KW - RISC-V
KW - ASIP
KW - Processor architecture
KW - Hardware architecture
KW - RISC-V
KW - ASIP
M3 - Paper
SP - 1
EP - 2
T2 - RISC-V Summit 2025 Europe
Y2 - 12 May 2025 through 15 May 2025
ER -