Details
| Original language | English |
|---|---|
| Title of host publication | 2025 20th International Conference on PhD Research in Microelectronics and Electronics, PRIME 2025 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (electronic) | 9798331503901 |
| ISBN (print) | 979-8-3315-0391-8 |
| Publication status | Published - 21 Sept 2025 |
| Event | 20th International Conference on PhD Research in Microelectronics and Electronics, PRIME 2025 - Taormina, Italy Duration: 21 Sept 2025 → 24 Sept 2025 |
Abstract
This work presents a low-distortion adderless switched-capacitor (SC) incremental delta-sigma modulator (I-Δ Σ M), where the reset in the SC circuit is applied for half a cycle, thereby achieving a zero-time reset from a system perspective. It is derived that the adderless low-distortion path is maintained as it effectively becomes an SC-adder path directly following the reset. The key innovation of this work lies in the combination of the adderless topology with the zero-time reset, along with the derivation of the inherently higher bandwidth of a half cycle reset system. In contrast to state-of-the-art (SOTA) I-Δ Σ M designs, which predominantly implement a full cycle reset, the zero-time reset yields valuable bandwidth. By means of a 2nd-order architecture, it is shown that the bandwidth increases by 12.5% at an oversampling ratio (OSR) of 8, while achieving nearly identical resolution. The concept is verified by simulation in a 55 nm CMOS technology. It is shown that neither the transmission gates nor limitations in the amplifiers impede the settling of the reset, which proves that the zero-time reset can be implemented in most SC-I- Δ Σ Ms designs to increase the bandwidth.
Keywords
- adderless, analog-to-digital, high-bandwidth, incremental delta-sigma, switched-capacitor, zero-time reset
ASJC Scopus subject areas
- Energy(all)
- Energy Engineering and Power Technology
- Engineering(all)
- Electrical and Electronic Engineering
- Physics and Astronomy(all)
- Instrumentation
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2025 20th International Conference on PhD Research in Microelectronics and Electronics, PRIME 2025. Institute of Electrical and Electronics Engineers Inc., 2025.
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - A Low-Distortion Adderless Zero-Time Reset Incremental Delta-Sigma Analog-to-Digital Converter
AU - Flemming, Jesko
AU - Tang, Kaxin
AU - Wicht, Bernhard
AU - Witte, Pascal
N1 - Publisher Copyright: © 2025 IEEE.
PY - 2025/9/21
Y1 - 2025/9/21
N2 - This work presents a low-distortion adderless switched-capacitor (SC) incremental delta-sigma modulator (I-Δ Σ M), where the reset in the SC circuit is applied for half a cycle, thereby achieving a zero-time reset from a system perspective. It is derived that the adderless low-distortion path is maintained as it effectively becomes an SC-adder path directly following the reset. The key innovation of this work lies in the combination of the adderless topology with the zero-time reset, along with the derivation of the inherently higher bandwidth of a half cycle reset system. In contrast to state-of-the-art (SOTA) I-Δ Σ M designs, which predominantly implement a full cycle reset, the zero-time reset yields valuable bandwidth. By means of a 2nd-order architecture, it is shown that the bandwidth increases by 12.5% at an oversampling ratio (OSR) of 8, while achieving nearly identical resolution. The concept is verified by simulation in a 55 nm CMOS technology. It is shown that neither the transmission gates nor limitations in the amplifiers impede the settling of the reset, which proves that the zero-time reset can be implemented in most SC-I- Δ Σ Ms designs to increase the bandwidth.
AB - This work presents a low-distortion adderless switched-capacitor (SC) incremental delta-sigma modulator (I-Δ Σ M), where the reset in the SC circuit is applied for half a cycle, thereby achieving a zero-time reset from a system perspective. It is derived that the adderless low-distortion path is maintained as it effectively becomes an SC-adder path directly following the reset. The key innovation of this work lies in the combination of the adderless topology with the zero-time reset, along with the derivation of the inherently higher bandwidth of a half cycle reset system. In contrast to state-of-the-art (SOTA) I-Δ Σ M designs, which predominantly implement a full cycle reset, the zero-time reset yields valuable bandwidth. By means of a 2nd-order architecture, it is shown that the bandwidth increases by 12.5% at an oversampling ratio (OSR) of 8, while achieving nearly identical resolution. The concept is verified by simulation in a 55 nm CMOS technology. It is shown that neither the transmission gates nor limitations in the amplifiers impede the settling of the reset, which proves that the zero-time reset can be implemented in most SC-I- Δ Σ Ms designs to increase the bandwidth.
KW - adderless
KW - analog-to-digital
KW - high-bandwidth
KW - incremental delta-sigma
KW - switched-capacitor
KW - zero-time reset
UR - http://www.scopus.com/inward/record.url?scp=105021555560&partnerID=8YFLogxK
U2 - 10.1109/PRIME66228.2025.11203575
DO - 10.1109/PRIME66228.2025.11203575
M3 - Conference contribution
AN - SCOPUS:105021555560
SN - 979-8-3315-0391-8
BT - 2025 20th International Conference on PhD Research in Microelectronics and Electronics, PRIME 2025
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 20th International Conference on PhD Research in Microelectronics and Electronics, PRIME 2025
Y2 - 21 September 2025 through 24 September 2025
ER -