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Institute of Microelectronic Systems

Organisational unit: Institute

Type of address: Visitor address.
Appelstraße 4
30167
Hannover
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Publications

  1. 2005
  2. Published

    HiBRID-SoC: A multi-core SoC architecture for multimedia signal processing

    Stolberg, H. J., Bereković, M., Moch, S., Friebe, L., Kulaczewski, M. B., Flügel, S., Klußmann, H., Dehnhardt, A. & Pirsch, P., 1 Aug 2005, In: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology. 41, 1, p. 9-20 12 p.

    Research output: Contribution to journalArticleResearchpeer review

  3. Published

    A methodology for modeling lateral parasitic transistors in smart power ICs

    Oehmen, J., Hedrich, L., Olbrich, M. & Barke, E., 2005, BMAS 2005 - Proceedings of the 2005 IEEE International Behavioral Modeling and Simulation Workshop. p. 19-24 6 p. 1518181. (BMAS 2005 - Proceedings of the 2005 IEEE International Behavioral Modeling and Simulation Workshop; vol. 2005).

    Research output: Chapter in book/report/conference proceedingConference contributionResearchpeer review

  4. Published

    A multi-core SoC design for advanced image and video compression

    Dehnhardt, A., Kulaczewski, M. B., Friebe, L., Moch, S., Pirsch, P., Stolberg, H. J. & Reuter, C., 2005, 2005 IEEE ICASSP '05 - Proc. : Design and Implementation of Signal Proces.Syst.,Indust. Technol. Track,Machine Learning for Signal Proces. Education, Spec. Sessions. Institute of Electrical and Electronics Engineers Inc., p. V665-V668 1416391. (ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings; vol. V).

    Research output: Chapter in book/report/conference proceedingConference contributionResearchpeer review

  5. Published

    Detailed routing with integrated static timing analysis applying simulated annealing

    Panitz, P., Olbrich, M. & Barke, E., 2005, 3rd International IEEE Northeast Workshop on Circuits and Systems Conference, NEWCAS 2005. p. 387-390 4 p. 1496696. (3rd International IEEE Northeast Workshop on Circuits and Systems Conference, NEWCAS 2005; vol. 2005).

    Research output: Chapter in book/report/conference proceedingConference contributionResearchpeer review

  6. Published

    Model-based exploration of the design space for heterogeneous systems on chip

    Blume, H., Feldkaemper, H. & Noll, T., 2005, In: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology.

    Research output: Contribution to journalArticleResearchpeer review

  7. Published

    Modeling substrate currents in smart power ICs

    Oehmen, J., Olbrich, M. & Barke, E., 2005, In: Proceedings of the International Symposium on Power Semiconductor Devices and ICs. p. 127-130 4 p., IP-P5.

    Research output: Contribution to journalConference articleResearchpeer review

  8. Published

    Net order optimization in analog net bundles

    Jambor, T., Schreiner, L., Olbrich, M. & Barke, E., 2005, In: Microtechnologies for New Millenium 2005.

    Research output: Contribution to journalArticleResearchpeer review

  9. Published

    PARSY: A PARasitic SYmetric router for net bundles using module generators

    Schreiner, L., Olbrich, M., Barke, E. & Meyer Zu Bexten, V., 2005, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT). p. 71-74 4 p. 1500023. (2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT); vol. 2005).

    Research output: Chapter in book/report/conference proceedingConference contributionResearchpeer review

  10. Published

    RAPANUI: Rapid prototyping for media processor architecture exploration

    Payá Vayá, G., Langerwerf, J. M. & Pirsch, P., 2005, In: Lecture Notes in Computer Science. 3553, p. 32-40 9 p.

    Research output: Contribution to journalConference articleResearchpeer review

  11. Published

    Routing of analog busses with parasitic symmetry.

    Schreiner, L. A., Olbrich, M., Barke, E. & Bexten, V. M. Z., 2005, p. 14-19.

    Research output: Contribution to conferencePaperResearchpeer review

  12. Published

    Von abstrakten Architekturtemplates zur hardwarenahen Architekturexploration

    Winter, M. & Pirsch, P., 2005, INFORMATIK 2005 - Informatik LIVE!, Beitrage der 35. Jahrestagung der Gesellschaft fur Informatik e.V. (GI). p. 458 1 p. (INFORMATIK 2005 - Informatik LIVE!, Beitrage der 35. Jahrestagung der Gesellschaft fur Informatik e.V. (GI); vol. 1).

    Research output: Chapter in book/report/conference proceedingConference contributionResearchpeer review

  13. 2004
  14. Published

    A coprocessor for intelligent image and video processing in the automotive and mobile communication domain

    Jachalsky, J., Wahle, M., Pirsch, P., Gehrke, W. & Hinz, T., 2004, 2004 IEEE International Symposium on Consumer Electronics - Proceedings. p. 142-145 4 p. (2004 IEEE International Symposium on Consumer Electronics - Proceedings).

    Research output: Chapter in book/report/conference proceedingConference contributionResearchpeer review

  15. Published

    Performance estimation of streaming media applications for reconfigurable platforms

    Reuter, C., Langerwerf, J. M., Stolberg, H. J. & Pirsch, P., 2004, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Pimentel, A. D. & Vassiliadis, S. (eds.). Springer Verlag, p. 69-77 9 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 3133).

    Research output: Chapter in book/report/conference proceedingContribution to book/anthologyResearchpeer review

  16. Published

    Placement Using a Localization Probability Model (LPM).

    Olbrich, M. & Barke, E., 2004, p. 1412.

    Research output: Contribution to conferencePaperResearchpeer review

  17. Published

    Wirelength Reduction Using 3-D Physical Design.

    Kaya, I., Salewski, S., Olbrich, M. & Barke, E., 2004, p. 453-462.

    Research output: Contribution to conferencePaperResearchpeer review

  18. 2003
  19. Published

    A scalable, clustered SMT processor for digital signal processing

    Berekovic, M., Moch, S. & Pirsch, P., 27 Sept 2003, p. 62-69. 8 p.

    Research output: Contribution to conferencePaperResearchpeer review

  20. Published

    HIBRID-SOC: A multi-core architecture for image and video applications

    Moch, S., Bereković, M., Stolberg, H. J., Friebe, L., Kulaczewski, M. B., Dehnhardt, A. & Pirsch, P., 27 Sept 2003, p. 55-61. 7 p.

    Research output: Contribution to conferencePaperResearchpeer review

  21. Published

    HiBRID-SoC: A multi-core SoC architecture for multimedia signal processing

    Stolberg, H. J., Bereković, M., Friebe, L., Moch, S., Kulaczewski, M. B., Dehnhardt, A. & Pirsch, P., 27 Aug 2003, 2003 IEEE Workshop on Signal Processing Systems: Design and Implementation, SIPS 2003. Sung, W. & Sunwoo, M. H. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 189-194 6 p. 1235667. (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation; vol. 2003-January).

    Research output: Chapter in book/report/conference proceedingConference contributionResearchpeer review

  22. Published

    Current Sense Amplifiers

    Wicht, B., 1 Jan 2003

    Research output: Book/ReportMonographResearchpeer review

  23. Published

    3-D placement considering vertical interconnects

    Kaya, I., Olbrich, M. & Barke, E., 2003, Proceedings - IEEE International SOC Conference, SOCC 2003. Ha, D. S., Auletta, R. & Chickanosky, J. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 257-258 2 p. 1241509. (Proceedings - IEEE International SOC Conference, SOCC 2003).

    Research output: Chapter in book/report/conference proceedingConference contributionResearchpeer review