Details
| Originalsprache | Englisch |
|---|---|
| Seiten | 55-61 |
| Seitenumfang | 7 |
| Publikationsstatus | Veröffentlicht - 27 Sept. 2003 |
| Veranstaltung | 2003 Workshop on Memory Performance: Dealing with Applications, Systems and Architecture, MEDEA '03 - Antibes Juan-les-Pins, Frankreich Dauer: 29 Sept. 2004 → 3 Okt. 2004 |
Konferenz
| Konferenz | 2003 Workshop on Memory Performance: Dealing with Applications, Systems and Architecture, MEDEA '03 |
|---|---|
| Land/Gebiet | Frankreich |
| Ort | Antibes Juan-les-Pins |
| Zeitraum | 29 Sept. 2004 → 3 Okt. 2004 |
Abstract
The HiBRID-SoC multi-core architecture targets a wide range of application fields with particularly high processing demands, including general signal processing applications, video de-encoding, image processing, or a combination of these tasks. For this purpose, the HiBRID-SoC integrates three fully programmable processor cores and various interfaces on a single chip, all tied to a 64-Bit AMBA AHB bus. Its memory subsystem is particularly adapted to the high bandwidth demands of the multi-core architecture by providing several DMA capabilities and multiple data transfer paths. The processor cores are individually optimized to the particular computational characteristics of different application fields, complementing each other to deliver high performance levels with high flexibility at reduced system costs. The HiBRID-SoC is fabricated in a 0.18 μm 6LM standard-cell technology, occupies about 82 mm2, operates at 145 MHz, and comsumes 3.5 Watts.
ASJC Scopus Sachgebiete
- Informatik (insg.)
- Angewandte Informatik
- Informatik (insg.)
- Hardware und Architektur
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
Zitieren
- Standard
- Harvard
- Apa
- Vancouver
- BibTex
- RIS
2003. 55-61 Beitrag in 2003 Workshop on Memory Performance: Dealing with Applications, Systems and Architecture, MEDEA '03, Antibes Juan-les-Pins, Frankreich.
Publikation: Konferenzbeitrag › Paper › Forschung › Peer-Review
}
TY - CONF
T1 - HIBRID-SOC
T2 - 2003 Workshop on Memory Performance: Dealing with Applications, Systems and Architecture, MEDEA '03
AU - Moch, S.
AU - Bereković, M.
AU - Stolberg, H. J.
AU - Friebe, L.
AU - Kulaczewski, M. B.
AU - Dehnhardt, A.
AU - Pirsch, P.
PY - 2003/9/27
Y1 - 2003/9/27
N2 - The HiBRID-SoC multi-core architecture targets a wide range of application fields with particularly high processing demands, including general signal processing applications, video de-encoding, image processing, or a combination of these tasks. For this purpose, the HiBRID-SoC integrates three fully programmable processor cores and various interfaces on a single chip, all tied to a 64-Bit AMBA AHB bus. Its memory subsystem is particularly adapted to the high bandwidth demands of the multi-core architecture by providing several DMA capabilities and multiple data transfer paths. The processor cores are individually optimized to the particular computational characteristics of different application fields, complementing each other to deliver high performance levels with high flexibility at reduced system costs. The HiBRID-SoC is fabricated in a 0.18 μm 6LM standard-cell technology, occupies about 82 mm2, operates at 145 MHz, and comsumes 3.5 Watts.
AB - The HiBRID-SoC multi-core architecture targets a wide range of application fields with particularly high processing demands, including general signal processing applications, video de-encoding, image processing, or a combination of these tasks. For this purpose, the HiBRID-SoC integrates three fully programmable processor cores and various interfaces on a single chip, all tied to a 64-Bit AMBA AHB bus. Its memory subsystem is particularly adapted to the high bandwidth demands of the multi-core architecture by providing several DMA capabilities and multiple data transfer paths. The processor cores are individually optimized to the particular computational characteristics of different application fields, complementing each other to deliver high performance levels with high flexibility at reduced system costs. The HiBRID-SoC is fabricated in a 0.18 μm 6LM standard-cell technology, occupies about 82 mm2, operates at 145 MHz, and comsumes 3.5 Watts.
UR - http://www.scopus.com/inward/record.url?scp=77953576862&partnerID=8YFLogxK
U2 - 10.1145/1152923.1024303
DO - 10.1145/1152923.1024303
M3 - Paper
AN - SCOPUS:77953576862
SP - 55
EP - 61
Y2 - 29 September 2004 through 3 October 2004
ER -