Details
| Originalsprache | Englisch |
|---|---|
| Titel des Sammelwerks | ICCSC'02. 1st IEEE International Conference on Circuits and Systems for Communications |
| Untertitel | Proceedings (IEEE Cat. No.02EX605) |
| Herausgeber/-innen | A. S. Korotkov |
| Herausgeber (Verlag) | Institute of Electrical and Electronics Engineers Inc. |
| Seiten | 190-193 |
| Seitenumfang | 4 |
| ISBN (Print) | 5742202601 |
| Publikationsstatus | Veröffentlicht - 7 Nov. 2002 |
| Extern publiziert | Ja |
| Veranstaltung | 1st IEEE International Conference on Circuits and Systems for Communications, ICCSC 2002 - St.Petersburg, Russland Dauer: 26 Juni 2002 → 28 Juni 2002 |
Abstract
One of the most challenging design issues for next generations of (mobile) communication systems is fulfilling the computational demands while finding an optimum trade-off between flexibility and implementation aspects, especially power consumption. Flexibility of modern architectures is desirable, e.g. concerning adaptation to new standards and reduction of time-to-market of a new product. Typical target architectures for future systems on chip include embedded FPGAs, dedicated macros as well as programmable digital signal and control oriented processor cores as each of these has its specific advantages. For such a heterogeneous architecture optimum partitioning plays a crucial role. On the exemplary vehicle of a Viterbi decoder as frequently used in communication systems we show which costs in terms of ATE complexity arise implementing typical components on different types of architecture blocks. Extending this comparison to further components, it is shown quantitatively that the cost ratio between different implementation alternatives is closely related to the operation to be performed. This information is essential for optimum partitioning of heterogeneous systems.
ASJC Scopus Sachgebiete
- Informatik (insg.)
- Computernetzwerke und -kommunikation
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
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ICCSC'02. 1st IEEE International Conference on Circuits and Systems for Communications: Proceedings (IEEE Cat. No.02EX605). Hrsg. / A. S. Korotkov. Institute of Electrical and Electronics Engineers Inc., 2002. S. 190-193.
Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review
}
TY - GEN
T1 - Analysis of reconfigurable and heterogeneous architectures in the communication domain
AU - Feldkämper, H. T.
AU - Gemmeke, T.
AU - Blume, H.
AU - Noll, T. G.
PY - 2002/11/7
Y1 - 2002/11/7
N2 - One of the most challenging design issues for next generations of (mobile) communication systems is fulfilling the computational demands while finding an optimum trade-off between flexibility and implementation aspects, especially power consumption. Flexibility of modern architectures is desirable, e.g. concerning adaptation to new standards and reduction of time-to-market of a new product. Typical target architectures for future systems on chip include embedded FPGAs, dedicated macros as well as programmable digital signal and control oriented processor cores as each of these has its specific advantages. For such a heterogeneous architecture optimum partitioning plays a crucial role. On the exemplary vehicle of a Viterbi decoder as frequently used in communication systems we show which costs in terms of ATE complexity arise implementing typical components on different types of architecture blocks. Extending this comparison to further components, it is shown quantitatively that the cost ratio between different implementation alternatives is closely related to the operation to be performed. This information is essential for optimum partitioning of heterogeneous systems.
AB - One of the most challenging design issues for next generations of (mobile) communication systems is fulfilling the computational demands while finding an optimum trade-off between flexibility and implementation aspects, especially power consumption. Flexibility of modern architectures is desirable, e.g. concerning adaptation to new standards and reduction of time-to-market of a new product. Typical target architectures for future systems on chip include embedded FPGAs, dedicated macros as well as programmable digital signal and control oriented processor cores as each of these has its specific advantages. For such a heterogeneous architecture optimum partitioning plays a crucial role. On the exemplary vehicle of a Viterbi decoder as frequently used in communication systems we show which costs in terms of ATE complexity arise implementing typical components on different types of architecture blocks. Extending this comparison to further components, it is shown quantitatively that the cost ratio between different implementation alternatives is closely related to the operation to be performed. This information is essential for optimum partitioning of heterogeneous systems.
KW - heterogeneous architectures
KW - partitioning
KW - reconfigurable systems
KW - Viterbi decoder
UR - http://www.scopus.com/inward/record.url?scp=84990882958&partnerID=8YFLogxK
U2 - 10.1109/OCCSC.2002.1029077
DO - 10.1109/OCCSC.2002.1029077
M3 - Conference contribution
AN - SCOPUS:84990882958
SN - 5742202601
SP - 190
EP - 193
BT - ICCSC'02. 1st IEEE International Conference on Circuits and Systems for Communications
A2 - Korotkov, A. S.
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 1st IEEE International Conference on Circuits and Systems for Communications, ICCSC 2002
Y2 - 26 June 2002 through 28 June 2002
ER -