Details
| Originalsprache | Englisch |
|---|---|
| Titel des Sammelwerks | 2025 23rd IEEE Interregional NEWCAS Conference (NEWCAS) |
| Seiten | 480-484 |
| Seitenumfang | 5 |
| ISBN (elektronisch) | 979-8-3315-3256-7 |
| Publikationsstatus | Veröffentlicht - 22 Juni 2025 |
Abstract
The current trend toward distributed microelectronic systems is creating new challenges for hardware architectures. Functional blocks that used to reside on a single chip now need to communicate across chip boundaries with limited pin availability and data integrity risks. AMBA AXI is a widely used standard for on-chip communication between such functional blocks, and due to its scope not designed for offchip communication. We therefore present the open-source Serial Transparent AXI-Bridge protocol, which aims to bridge between two AXI networks by serializing messages, thereby increasing line utilization with minimal performance impact. The reduction to one channel per direction, along with the mode change from a transaction-based to a stream-based communication approach, reduces the number of pins required and prepares for further more standardized serialization methods. It remains transparent to the AXI members, allowing it to be deployed without modification to existing modules, while providing data integrity robustness improvements. We also present real-world data from an FPGA design that transfers data over a loopback card using a open-source VHDL reference implementation.
ASJC Scopus Sachgebiete
- Physik und Astronomie (insg.)
- Instrumentierung
- Informatik (insg.)
- Artificial intelligence
- Informatik (insg.)
- Maschinelles Sehen und Mustererkennung
- Informatik (insg.)
- Hardware und Architektur
- Energie (insg.)
- Energieanlagenbau und Kraftwerkstechnik
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
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2025 23rd IEEE Interregional NEWCAS Conference (NEWCAS). 2025. S. 480-484.
Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review
}
TY - GEN
T1 - A Serial Transparent AXI Bridge for Cross-Chip Integration
AU - Fiedler, Till
AU - Marten, Jakob
AU - Langhorst, Dominik
AU - Blume, Holger
N1 - Publisher Copyright: © 2025 IEEE.
PY - 2025/6/22
Y1 - 2025/6/22
N2 - The current trend toward distributed microelectronic systems is creating new challenges for hardware architectures. Functional blocks that used to reside on a single chip now need to communicate across chip boundaries with limited pin availability and data integrity risks. AMBA AXI is a widely used standard for on-chip communication between such functional blocks, and due to its scope not designed for offchip communication. We therefore present the open-source Serial Transparent AXI-Bridge protocol, which aims to bridge between two AXI networks by serializing messages, thereby increasing line utilization with minimal performance impact. The reduction to one channel per direction, along with the mode change from a transaction-based to a stream-based communication approach, reduces the number of pins required and prepares for further more standardized serialization methods. It remains transparent to the AXI members, allowing it to be deployed without modification to existing modules, while providing data integrity robustness improvements. We also present real-world data from an FPGA design that transfers data over a loopback card using a open-source VHDL reference implementation.
AB - The current trend toward distributed microelectronic systems is creating new challenges for hardware architectures. Functional blocks that used to reside on a single chip now need to communicate across chip boundaries with limited pin availability and data integrity risks. AMBA AXI is a widely used standard for on-chip communication between such functional blocks, and due to its scope not designed for offchip communication. We therefore present the open-source Serial Transparent AXI-Bridge protocol, which aims to bridge between two AXI networks by serializing messages, thereby increasing line utilization with minimal performance impact. The reduction to one channel per direction, along with the mode change from a transaction-based to a stream-based communication approach, reduces the number of pins required and prepares for further more standardized serialization methods. It remains transparent to the AXI members, allowing it to be deployed without modification to existing modules, while providing data integrity robustness improvements. We also present real-world data from an FPGA design that transfers data over a loopback card using a open-source VHDL reference implementation.
KW - axi
KW - communication
KW - computer architecture
KW - fpga
KW - inter-chip
KW - protocols
UR - http://www.scopus.com/inward/record.url?scp=105015559601&partnerID=8YFLogxK
U2 - 10.1109/newcas64648.2025.11107161
DO - 10.1109/newcas64648.2025.11107161
M3 - Conference contribution
SN - 979-8-3315-3257-4
SP - 480
EP - 484
BT - 2025 23rd IEEE Interregional NEWCAS Conference (NEWCAS)
ER -