Details
| Originalsprache | Englisch |
|---|---|
| Seiten (von - bis) | 215-231 |
| Seitenumfang | 17 |
| Fachzeitschrift | Journal of Signal Processing Systems |
| Jahrgang | 58 |
| Ausgabenummer | 2 |
| Publikationsstatus | Veröffentlicht - 20 März 2009 |
Abstract
The available instruction level parallelism allowed by current register file organizations is not always fully exploited by media processors when running a multimedia application. This paper introduces a novel register file organization, called multi-shared register file, that eliminates this superfluous instruction scheduling flexibility by reducing the number of read and write ports and partitioning the register file in a special ring structure. A parameterized generic VLIW architecture is used to explore different configurations of our proposed register file structure in terms of estimated silicon area, minimum clock period, estimated power consumption, and multimedia task processing performance. Moreover, a metric highly related to multimedia applications is introduced to study trade-offs between hardware cost and performance. The results show that by substituting a monolithic register file with an equivalent multi-shared register file, the estimated area and the power consumption are considerably reduced at the cost of a negligible performance degradation.
ASJC Scopus Sachgebiete
- Ingenieurwesen (insg.)
- Steuerungs- und Systemtechnik
- Mathematik (insg.)
- Theoretische Informatik
- Informatik (insg.)
- Signalverarbeitung
- Informatik (insg.)
- Information systems
- Mathematik (insg.)
- Modellierung und Simulation
- Informatik (insg.)
- Hardware und Architektur
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in: Journal of Signal Processing Systems, Jahrgang 58, Nr. 2, 20.03.2009, S. 215-231.
Publikation: Beitrag in Fachzeitschrift › Artikel › Forschung › Peer-Review
}
TY - JOUR
T1 - A multi-shared register file structure for VLIW processors
AU - Payá-Vayá, Guillermo
AU - Martín-Langerwerf, Javier
AU - Pirsch, Peter
PY - 2009/3/20
Y1 - 2009/3/20
N2 - The available instruction level parallelism allowed by current register file organizations is not always fully exploited by media processors when running a multimedia application. This paper introduces a novel register file organization, called multi-shared register file, that eliminates this superfluous instruction scheduling flexibility by reducing the number of read and write ports and partitioning the register file in a special ring structure. A parameterized generic VLIW architecture is used to explore different configurations of our proposed register file structure in terms of estimated silicon area, minimum clock period, estimated power consumption, and multimedia task processing performance. Moreover, a metric highly related to multimedia applications is introduced to study trade-offs between hardware cost and performance. The results show that by substituting a monolithic register file with an equivalent multi-shared register file, the estimated area and the power consumption are considerably reduced at the cost of a negligible performance degradation.
AB - The available instruction level parallelism allowed by current register file organizations is not always fully exploited by media processors when running a multimedia application. This paper introduces a novel register file organization, called multi-shared register file, that eliminates this superfluous instruction scheduling flexibility by reducing the number of read and write ports and partitioning the register file in a special ring structure. A parameterized generic VLIW architecture is used to explore different configurations of our proposed register file structure in terms of estimated silicon area, minimum clock period, estimated power consumption, and multimedia task processing performance. Moreover, a metric highly related to multimedia applications is introduced to study trade-offs between hardware cost and performance. The results show that by substituting a monolithic register file with an equivalent multi-shared register file, the estimated area and the power consumption are considerably reduced at the cost of a negligible performance degradation.
KW - Design space exploration
KW - Media processor
KW - Register file
KW - VLIW
UR - http://www.scopus.com/inward/record.url?scp=77951205533&partnerID=8YFLogxK
U2 - 10.1007/s11265-009-0355-2
DO - 10.1007/s11265-009-0355-2
M3 - Article
AN - SCOPUS:77951205533
VL - 58
SP - 215
EP - 231
JO - Journal of Signal Processing Systems
JF - Journal of Signal Processing Systems
SN - 1939-8018
IS - 2
ER -