A Hardware Efficient Digital DAC Linearization Topology for Delta-Sigma ADCs

Publikation: Beitrag in Buch/Bericht/Sammelwerk/KonferenzbandAufsatz in KonferenzbandForschungPeer-Review

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  • Hochschule Hannover (HsH)
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OriginalspracheEnglisch
Titel des SammelwerksProceedings - 2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2024
Herausgeber (Verlag)Institute of Electrical and Electronics Engineers Inc.
ISBN (elektronisch)9798350351927
ISBN (Print)979-8-3503-5193-4
PublikationsstatusVeröffentlicht - 2 Juli 2024
Veranstaltung20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2024 - Volos, Griechenland
Dauer: 2 Juli 20245 Juli 2024

Publikationsreihe

NameInternational Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design
ISSN (elektronisch)2575-4890

Abstract

This paper presents a digital topology for linearizing multi-bit feedback digital-to-analog converters (DACs) in delta-sigma modulators (Δ Σ Ms). The proposed topology significantly surpasses existing techniques in hardware utilization, efficiency, and implementation effort by simplifying the complex digital transfer functions in the digital linearization system to a gain-only transfer function and by sparing an explicit adder for the mismatch correction. These simplifications still allow an almost ideal linearization of the overall system, improving our exemplary Δ Σ M by more than 30dB in spurious free dynamic range (SFDR) as well as 33dB in signal to noise and distortion ratio (SNDR). Furthermore, the technique's hardware utilization is reduced by almost 50% compared to techniques utilizing complex transfer functions for the digital linearization. The presented linearization topology offers a practical and efficient solution for high-bandwidth systems reducing the implementation effort as well as the power consumption.

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A Hardware Efficient Digital DAC Linearization Topology for Delta-Sigma ADCs. / Flemming, Jesko; Rogge, Timon; Wicht, Bernhard et al.
Proceedings - 2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2024. Institute of Electrical and Electronics Engineers Inc., 2024. (International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design).

Publikation: Beitrag in Buch/Bericht/Sammelwerk/KonferenzbandAufsatz in KonferenzbandForschungPeer-Review

Flemming, J, Rogge, T, Wicht, B & Witte, P 2024, A Hardware Efficient Digital DAC Linearization Topology for Delta-Sigma ADCs. in Proceedings - 2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2024. International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Institute of Electrical and Electronics Engineers Inc., 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2024, Volos, Griechenland, 2 Juli 2024. https://doi.org/10.1109/SMACD61181.2024.10745378
Flemming, J., Rogge, T., Wicht, B., & Witte, P. (2024). A Hardware Efficient Digital DAC Linearization Topology for Delta-Sigma ADCs. In Proceedings - 2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2024 (International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SMACD61181.2024.10745378
Flemming J, Rogge T, Wicht B, Witte P. A Hardware Efficient Digital DAC Linearization Topology for Delta-Sigma ADCs. in Proceedings - 2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2024. Institute of Electrical and Electronics Engineers Inc. 2024. (International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design). doi: 10.1109/SMACD61181.2024.10745378
Flemming, Jesko ; Rogge, Timon ; Wicht, Bernhard et al. / A Hardware Efficient Digital DAC Linearization Topology for Delta-Sigma ADCs. Proceedings - 2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2024. Institute of Electrical and Electronics Engineers Inc., 2024. (International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design).
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abstract = "This paper presents a digital topology for linearizing multi-bit feedback digital-to-analog converters (DACs) in delta-sigma modulators (Δ Σ Ms). The proposed topology significantly surpasses existing techniques in hardware utilization, efficiency, and implementation effort by simplifying the complex digital transfer functions in the digital linearization system to a gain-only transfer function and by sparing an explicit adder for the mismatch correction. These simplifications still allow an almost ideal linearization of the overall system, improving our exemplary Δ Σ M by more than 30dB in spurious free dynamic range (SFDR) as well as 33dB in signal to noise and distortion ratio (SNDR). Furthermore, the technique's hardware utilization is reduced by almost 50% compared to techniques utilizing complex transfer functions for the digital linearization. The presented linearization topology offers a practical and efficient solution for high-bandwidth systems reducing the implementation effort as well as the power consumption.",
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T1 - A Hardware Efficient Digital DAC Linearization Topology for Delta-Sigma ADCs

AU - Flemming, Jesko

AU - Rogge, Timon

AU - Wicht, Bernhard

AU - Witte, Pascal

N1 - Publisher Copyright: © 2024 IEEE.

PY - 2024/7/2

Y1 - 2024/7/2

N2 - This paper presents a digital topology for linearizing multi-bit feedback digital-to-analog converters (DACs) in delta-sigma modulators (Δ Σ Ms). The proposed topology significantly surpasses existing techniques in hardware utilization, efficiency, and implementation effort by simplifying the complex digital transfer functions in the digital linearization system to a gain-only transfer function and by sparing an explicit adder for the mismatch correction. These simplifications still allow an almost ideal linearization of the overall system, improving our exemplary Δ Σ M by more than 30dB in spurious free dynamic range (SFDR) as well as 33dB in signal to noise and distortion ratio (SNDR). Furthermore, the technique's hardware utilization is reduced by almost 50% compared to techniques utilizing complex transfer functions for the digital linearization. The presented linearization topology offers a practical and efficient solution for high-bandwidth systems reducing the implementation effort as well as the power consumption.

AB - This paper presents a digital topology for linearizing multi-bit feedback digital-to-analog converters (DACs) in delta-sigma modulators (Δ Σ Ms). The proposed topology significantly surpasses existing techniques in hardware utilization, efficiency, and implementation effort by simplifying the complex digital transfer functions in the digital linearization system to a gain-only transfer function and by sparing an explicit adder for the mismatch correction. These simplifications still allow an almost ideal linearization of the overall system, improving our exemplary Δ Σ M by more than 30dB in spurious free dynamic range (SFDR) as well as 33dB in signal to noise and distortion ratio (SNDR). Furthermore, the technique's hardware utilization is reduced by almost 50% compared to techniques utilizing complex transfer functions for the digital linearization. The presented linearization topology offers a practical and efficient solution for high-bandwidth systems reducing the implementation effort as well as the power consumption.

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