TY - JOUR

T1 - A Cryo-BiCMOS Controller for Quantum Computers based on Trapped Beryllium Ions

AU - Toth, Peter

AU - Shine Eugine, Paul

AU - Kudabay, Yerzhan

AU - Yamashita, Kaoru

AU - Halama, Sebastian

AU - Parvizinejad, Judi

AU - Bonkowski, Marco

AU - Ishikuro, Hiroki

AU - Ospelkaus, Christian

AU - Issakov, Vadim

N1 - Publisher Copyright: © 1966-2012 IEEE.

PY - 2026/2

Y1 - 2026/2

N2 - This article presents a cryo-BiCMOS system on chip (SoC) designed for single and two-qubit gate operations for quantum computers (QCs) based on beryllium trapped-ions (TIs). Signal generation from 0.7 to 1.6 GHz is supported, covering all microwave transitions in a 9Be+ QC realization. An integrated 48-kbit waveform memory is implemented for improved two-qubit gate fidelity. The fabricated IC is verified in a 4 K environment with up to 4 qubits, thus enabling quantum processor unit (QPU) cointegration. IC operation up to RT ensures compatibility with future system realizations. Measurements demonstrate qubit state control with an oscillation amplitude of 94% before SPAM correction and Rabi oscillation rate of 172 kHz. Evaluations of long sequences of σx gates indicate control of the quantum state with high quality. Interaction with one computational zone is possible at a total power consumption of 86 mW translating to 21.5 mW/qubit in the presented measurements. Comparison with the state-of-the-art controller reveals drastic power and form-factor reduction at comparable performance, thus paving the way for a scalable TI platform. The chip is fabricated in a 0.13-μm SiGe BiCMOS technology. To the best of our knowledge, this is the first reported from-scratch system design for TI-based QC concluding with a qubit state manipulation demonstration.

AB - This article presents a cryo-BiCMOS system on chip (SoC) designed for single and two-qubit gate operations for quantum computers (QCs) based on beryllium trapped-ions (TIs). Signal generation from 0.7 to 1.6 GHz is supported, covering all microwave transitions in a 9Be+ QC realization. An integrated 48-kbit waveform memory is implemented for improved two-qubit gate fidelity. The fabricated IC is verified in a 4 K environment with up to 4 qubits, thus enabling quantum processor unit (QPU) cointegration. IC operation up to RT ensures compatibility with future system realizations. Measurements demonstrate qubit state control with an oscillation amplitude of 94% before SPAM correction and Rabi oscillation rate of 172 kHz. Evaluations of long sequences of σx gates indicate control of the quantum state with high quality. Interaction with one computational zone is possible at a total power consumption of 86 mW translating to 21.5 mW/qubit in the presented measurements. Comparison with the state-of-the-art controller reveals drastic power and form-factor reduction at comparable performance, thus paving the way for a scalable TI platform. The chip is fabricated in a 0.13-μm SiGe BiCMOS technology. To the best of our knowledge, this is the first reported from-scratch system design for TI-based QC concluding with a qubit state manipulation demonstration.

KW - BiCMOS

KW - cryo-BiCMOS

KW - cryogenic

KW - direct digital synthesis (DDS)

KW - quantum computing

KW - qubit control

KW - trapped-ions

UR - http://www.scopus.com/inward/record.url?scp=105024422041&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2025.3632204

DO - 10.1109/JSSC.2025.3632204

M3 - Article

AN - SCOPUS:105024422041

VL - 61

SP - 673

EP - 689

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 2

ER -